Active DI Schematic Capture
JP_GLB from the schematic. I verified the checked ERC/DRC categories are still clean, and updated Schematic Capture Notes to record the GLB removal.A0 and CHASSIS remain separate elsewhere; connector shield/chassis terminations were not changed.Diagram
Table
| Interface | Signals / Nets |
|---|---|
| Input jack | J_IN_TIP, A0_INPUT |
| Thru jack | J_THRU_TIP hardwired to input tip, A0_INPUT sleeve |
| Input load switch | Low side of R_Z_HIGH, R_Z_NORMAL, R_Z_LOW, common to A0_INPUT, one open position |
| HPF switch | BUF_OUT and HPF_N1 commons; capacitor-bank throws to HPF_N1/HPF_N2 |
| Master pot | LEVEL_TOP, LEVEL_WIPER, A0 |
| XLR output | XLR_2, XLR_3, pin 1 to CHASSIS |
| TRS output | TRS_TIP, TRS_RING, sleeve to CHASSIS |
| Mains / PSU | PE, CHASSIS, +15V_RAW, -15V_RAW, A0_PSU |
Diagram
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Input / Thru / Protection
Input Loading
Buffer and HPF
Output Stages
Power / Ground / Chassis
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Physical Design Expectations
Important Design Decisions
Assumptions
Open Review Gates
Change Notes