Thought for 1 sec — Determining component dimensions
Thought for 1 sec — Determining component dimensions
Moving footprints.
Thought for 20 sec
Moving footprints.
Thought for 2 sec
Thought for 1 min 3 sec
Moving footprints.
Thought for 13 sec — Considering coordinates and placement
Thought for a moment — Considering coordinates and placement
Moving footprints.
Moving footprints.
Thought for 4 sec
Thought for 1 sec — Addressing overlap issues
Thought for 1 sec — Addressing overlap issues
Moving footprints.
Thought for 6 sec
Thought for 6 sec — Exploring passive arrangement strategies
Thought for a moment — Exploring passive arrangement strategies
Thought for 2 sec — Arranging components efficiently
Thought for 5 sec — Arranging components efficiently
Thought for 15 sec — Considering mounting arrangements
Thought for a moment — Considering mounting arrangements
Thought for 1 sec — Arranging electronic components
Thought for 1 sec — Arranging electronic components
Moving footprints.
Thought for 43 sec
Moving footprints.
Moving footprints.
Thought for 1 sec
Thought for 11 sec
Thought for 10 sec — Rearranging grid components
Thought for a moment — Rearranging grid components
Thought for a moment
Reorganizing component layout
I might need to consider moving some components around to create better spacing. For example, I could put things far right between J_MPCIE and the top at coordinates x 40-60, y 28-42. I see options in the bottom-left, too, avoiding conflicts with J_BAT, J_SIM, and MH16. I could also look at center-left positions and lower center options. It's becoming clear that the initial manual zones might be too crowded, so I’ll need to adjust big connectors to the edges and reserve space for passives. Placing U_CM4 in the center could help.
I have rearrange the the board this is the finaly position of the cm4, mosiac and 4g modem - correct the io board mounting holes to match the offical io board hole locations as they are currently incorrect, also add/correct the fixings and mounts and holes for the m.2, cm4 and mpcie units to suit the quectel em05 and the mosiac, here are the data sheets.
I’ll preserve your manually placed CM4/Mosaic/4G positions, then correct only mechanical items: official CM4 IO mounting holes, CM4 mounting/fixing holes, and M.2/mPCIe standoff holes from the provided datasheets. I’ll source/inspect the official geometry before mutating holes.
Worked for 17 sec
50 days ago
1/4 Extract official CM4 IO mounting-hole coordinates and current layout hole state
Extract official CM4 IO mounting-hole coordinates and current layout hole state
Extract M.2 EM05 and simpleRTK3B mPCIe mechanical fixing requirements from datasheets
Correct/add board, CM4, M.2, and mPCIe mounting holes without moving CM4/Mosaic/LTE modules
Verify mechanical holes and document any remaining datasheet/footprint caveats
Keep the Power Architecture Hard Gate active, but do not block non-power schematic development while final battery and power-path details are gathered.
Recommended defaults for the next implementation pass:
BQ25750 design authority: use the latest official TI BQ25750 datasheet, BQ25750EVM User Guide Rev. B / SLUUCY7B, TI BQ25750 schematic/layout checklist, and TI E2E design-file threads as references. The editable EVM CAD files are useful but not mandatory.
PoE+ default: use a 12 V isolated IEEE 802.3at PoE+ module as the default intermediate rail.
Preferred external BOM target: Silvertel Ag5412 if we want the newer Ag5400 family.
Flux-library-available implementation part: Silvertel AG5300, 12 V / 2.5 A isolated PoE module, part UID dde9bf77-ffc7-4620-972a-a0a2d31f62fc.
24 V option: Silvertel Ag5424 if lower secondary-side current is worth the higher downstream voltage stress.
LTE default: give the Quectel EM05 its own 3.3 V / 3 A supply branch with local bulk capacitance and controlled power sequencing.
GNSS default: keep Mosaic/mini PCIe on a separate clean 3.3 V rail with filtering/load control isolated from LTE burst current.
Charging default: configure BQ25750 for 2S Li-ion / 8.4 V regulation, but keep charge current and compensation values provisional until the exact battery pack and TI-derived calculations are complete.
TI BQ25750 sources found
Table
Source
Status
How to use
TI BQ25750 product page
Found
Primary source for datasheet, product collateral, EVM, and design resources.
BQ25750EVM User Guide, SLUUCY7B, Rev. B, revised May 2025
TI E2E FAQ: BQ25750 Schematic and Layout Checklist
Found
Formal checklist before schematic/layout release. If checklist conflicts with datasheet, datasheet wins.
TI E2E design-file thread: BQ25750_EVM_Altium_Design_Files.zip
Found
Useful optional source if accessible. Not a blocker.
TI E2E ASCII design-file thread
Found
Optional alternative CAD reference if native files are difficult to import.
Important BQ25750EVM caveats
EVM is a lab evaluation board, not production hardware.
EVM limits: 55 V max input, 30 V max output, 10 A max charge current.
EVM defaults include 8 A input current, 10 A output current, and 250 kHz switching frequency.
EVM has no installed fuse and is not a complete product safety design.
The carrier design must independently validate FETs, inductor, current sense, compensation, thermal performance, clearances, fusing, reverse-current blocking, and battery safety.
TI checklist items that must be implemented/verified
Table
Circuit item
Requirement / extracted guidance
Buck/boost FETs
Four N-channel switching MOSFETs Q1-Q4 required. Gate drive resistors typically 0 ohm; no gate-source pulldowns unless TI says otherwise.
Bootstrap
Schottky bootstrap diodes; 100 nF bootstrap caps close to IC; DRV_SUP 4.7 uF close to IC.
Input protection FETs
Optional back-to-back input N-FETs; gate-source zener around 15 V if used.
Battery FETs
BATDRV drives N-channel battery FETs; gate-drive limiting resistor and turn-on cap per checklist/EVM.
Inductor
Required; checklist gives 2.2 uH min, 10 uH typical, 15 uH max range. Must be recalculated for this 2S UPS load/thermal case.
Input current sense
RAC optional, 0-5 mΩ. If not used, short ACP/ACN to VAC. For PoE/DC input limiting, RAC is likely useful.
Battery current sense
RBAT/SRP-SRN sense resistor is 5 mΩ fixed; different value not recommended by TI checklist. Kelvin route.
Real 10 k NTC such as 103AT-2 style network from REGN to TS to PGND; select divider values from BQ25750 datasheet JEITA section.
Layout
Minimize buck/boost switching loops; Kelvin sense resistors; keep sense traces away from switch nodes; analog ground plane tied to PGND under exposed pad; lowest-value bypass capacitors closest to IC.
Quectel EM05 hardware guide findings
Public source found: Quectel_EM05_Hardware_Design_V1.2-2.pdf, dated 2020-01-07. Official Quectel EM05 product page also lists EM05-G/EM05-E variant guides, with some downloads login-restricted.
EM05 power requirements
Table
Item
Requirement
VCC operating range
3.135 V to 4.4 V
Typical VCC
3.3 V
VCC pins
M.2 pins 2, 4, 70, 72, 74
Ground pins
3, 5, 11, 27, 33, 39, 45, 51, 57, 71, 73
Supply current capability
At least 2.0 A; reference supply supports 3.0 A
VCC droop warning
Must not fall below 3.135 V during burst transmission
Local VCC capacitance
220 uF low-ESR bulk plus 1 uF, 100 nF, 33 pF, 10 pF close to VCC pins
VCC TVS
Low clamp TVS; Quectel suggests VRWM 4.7 V class
VCC routing
Wide trace, about >= 2 mm where practical
Implementation implication: 3V3_LTE must be a dedicated regulator/load-switch branch sized for 3 A transient margin, not a shared logic rail.
EM05 USB requirements
Table
Item
Requirement
Interface
USB 2.0 device/slave
Speed
High-speed 480 Mbps
DP/DM impedance
90 ohm differential
ESD
Low-capacitance USB ESD, typically **=30 ms. Boot to active can take >=12 s.
RESET#
Pin 67; active low; pulse low 150-460 ms; no large capacitance on reset. Before forced shutdown, Quectel recommends pulling RESET# low around 100 ms to avoid flash damage.
W_DISABLE1#
Pin 8; active low RF disable; hardware control disabled by firmware by default and can be enabled using AT+QCFG="airplanecontrol".
PoE+ module options
Table
Candidate
Output
Power
Library status
Recommendation
Silvertel Ag5412
12 V / 2.5 A
30 W
Not found in Flux library
Preferred external BOM target if using Ag5400 family; request/add symbol if selected.
Silvertel Ag5424
24 V / 1.25 A
30 W
Not found in Flux library
Good alternate if 24 V intermediate bus is desired.
Silvertel AG5300
12 V / 2.5 A
30 W class
Found in Flux library
Best immediate implementation default because symbol exists.
Silvertel AG5712-LPB
12 V / 2.5 A
30 W
Not found in Flux library
Low-profile alternate; evaluate if height/area matters.
PoweredEthernet PEM3212
12 V
~24-30 W peak depending datasheet
Not found in Flux library
Secondary-source candidate; verify continuous output before use.
Silvertel Ag59812-LPB / Ag59824-LPB
12 V / 24 V
802.3bt high-power class
Not searched in library this pass
Upgrade path if PoE+ power budget is too tight.
Ag5400 family extracted constraints
IEEE 802.3at Type 2 Class 4 PD; backward compatible with 802.3af and usable in 802.3bt environments.
In compliant PoE+, PSE output may be 30 W but the PD can rely on about 25.5 W available after cable loss before module/downstream losses.
Ag5412 output: 12 V, 2.5 A, 30 W continuous.
Ag5424 output: 24 V, 1.25 A, 30 W continuous.
Isolation: 1500 Vdc input-to-output.
Efficiency: Ag5412 peak about 93.3%.
Operating temperature: -40°C to +85°C, but enclosure derating still required.
Output cap required close to output pins. Ag5412 recommendation: 220 uF minimum, 470 uF typical, 1000 uF max, low ESR suitable for low temperature.
If an auxiliary/external supply can drive the module output, Silvertel requires a blocking diode or equivalent to prevent output backfeed into the PoE module.
Default architecture after research
Text
RJ45 / Ethernet magnetics / PoE input
-> isolated 12 V PoE+ module, default AG5300 in Flux or Ag5412 external BOM target
-> reverse-current blocking / ideal-diode OR with external DC input
-> BQ25750 input / direct power-path / 2S charger, provisional until TI checklist complete
-> downstream rails:
5V_CM dedicated CM4 regulator
3V3_LTE dedicated 3 A LTE regulator/load switch
3V3_GNSS clean GNSS regulator/filter/load switch
3V3_HUB USB hub/logic rail
3V3_AUX low-current control/peripheral rail
Remaining documents / unresolved decisions before production-ready schematic