Project Redesign Brief


Worked for 5 mins 37 sec
Moving footprints.
Moving footprints.
Moving footprints.
Moving footprints.
Thought for a moment
Thought for 4 sec
Thought for a moment — Planning PCB layout
Thought for 1 sec — Planning PCB layout
Moving footprints.
Thought for 3 sec
Referenced guidance.
Moving footprints.
Thought for a moment
Thought for 5 sec
Moving footprints.
Moving footprints.
Thought for 3 sec
Thought for 2 sec
Thought for 1 sec — Determining component dimensions
Thought for 1 sec — Determining component dimensions
Moving footprints.
Thought for 20 sec
Moving footprints.
Thought for 2 sec
Thought for 1 min 3 sec
Moving footprints.
Thought for 13 sec — Considering coordinates and placement
Thought for a moment — Considering coordinates and placement
Moving footprints.
Moving footprints.
Thought for 4 sec
Thought for 1 sec — Addressing overlap issues
Thought for 1 sec — Addressing overlap issues
Moving footprints.
Thought for 6 sec
Thought for 6 sec — Exploring passive arrangement strategies
Thought for a moment — Exploring passive arrangement strategies
Thought for 2 sec — Arranging components efficiently
Thought for 5 sec — Arranging components efficiently
Thought for 15 sec — Considering mounting arrangements
Thought for a moment — Considering mounting arrangements
Thought for 1 sec — Arranging electronic components
Thought for 1 sec — Arranging electronic components
Moving footprints.
Thought for 43 sec
Moving footprints.
Moving footprints.
Thought for 1 sec
Thought for 11 sec
Thought for 10 sec — Rearranging grid components
Thought for a moment — Rearranging grid components
Thought for a moment
Reorganizing component layout
I might need to consider moving some components around to create better spacing. For example, I could put things far right between J_MPCIE and the top at coordinates x 40-60, y 28-42. I see options in the bottom-left, too, avoiding conflicts with J_BAT, J_SIM, and MH16. I could also look at center-left positions and lower center options. It's becoming clear that the initial manual zones might be too crowded, so I’ll need to adjust big connectors to the edges and reserve space for passives. Placing U_CM4 in the center could help.
I have rearrange the the board this is the finaly position of the cm4, mosiac and 4g modem - correct the io board mounting holes to match the offical io board hole locations as they are currently incorrect, also add/correct the fixings and mounts and holes for the m.2, cm4 and mpcie units to suit the quectel em05 and the mosiac, here are the data sheets.
I’ll preserve your manually placed CM4/Mosaic/4G positions, then correct only mechanical items: official CM4 IO mounting holes, CM4 mounting/fixing holes, and M.2/mPCIe standoff holes from the provided datasheets. I’ll source/inspect the official geometry before mutating holes.
Worked for 17 sec
1/4 Extract official CM4 IO mounting-hole coordinates and current layout hole state

Extract official CM4 IO mounting-hole coordinates and current layout hole state

Extract M.2 EM05 and simpleRTK3B mPCIe mechanical fixing requirements from datasheets

Correct/add board, CM4, M.2, and mPCIe mounting holes without moving CM4/Mosaic/LTE modules

Verify mechanical holes and document any remaining datasheet/footprint caveats

Thought for 14 sec — Considering file access
Referenced guidance.

U_DC_OR
D_ESD_USB_SERVICE
Y_HUB_24M
Resistance
60 ohms
D_ESD_USB_LTE
J_MPCIE_GNSS
U_CHG
D_ESD_USB_MOSAIC
U_AUX_LDO
U_POE_OR
PS_POE
D_POE_12V_TVS
P_PWR_GOOD
Pin Number
1
P_CHG_INT
Pin Number
1
P_ETH_TRD0_P
Pin Number
1
P_SIM_RST
Pin Number
1
P_GND
Pin Number
1
P_ETH_TRD3_N
Pin Number
1
P_SIM_CLK
Pin Number
1
P_LTE_USB_DP
Pin Number
1
P_ETH_TRD1_N
Pin Number
1
P_ETH_TRD1_P
Pin Number
1
P_ETH_TRD3_P
Pin Number
1
P_SIM_DATA
Pin Number
1
P_LTE_W_DISABLE
Pin Number
1
P_CHG_EN
Pin Number
1
P_SAFE_SHUTDOWN
Pin Number
1
P_FG_INT
Pin Number
1
P_BAT_NTC
Pin Number
1
P_MOSAIC_PWR_EN
Pin Number
1
P_SERVICE_USB_DP
Pin Number
1
P_LTE_USB_DM
Pin Number
1
P_ETH_TRD2_N
Pin Number
1
P_WD_HEARTBEAT
Pin Number
1
P_SIM_VCC
Pin Number
1
P_ETH_TRD2_P
Pin Number
1
P_I2C_SDA
Pin Number
1
P_MOSAIC_USB_DP
Pin Number
1
P_SIM_DET
Pin Number
1
P_CM_USB_DM
Pin Number
1
P_CM_RUN_RESET
Pin Number
1
P_I2C_SCL
Pin Number
1
P_5V_CM
Pin Number
1
P_3V3_AUX
Pin Number
1
P_BAT_2S
Pin Number
1
P_HUB_RESET
Pin Number
1
P_3V3_HUB
Pin Number
1
P_MOSAIC_USB_DM
Pin Number
1
P_MOSAIC_RESET
Pin Number
1
P_HUB_CLK
Pin Number
1
D_DC_IN_TVS
P_SYS_BUS
Pin Number
1
P_POE_RAW
Pin Number
1
P_3V3_GNSS
Pin Number
1
P_CM_USB_DP
Pin Number
1
P_3V3_LTE
Pin Number
1
P_LTE_PWR_EN
Pin Number
1
P_SERVICE_USB_DM
Pin Number
1
P_DC_RAW
Pin Number
1
P_ETH_TRD0_N
Pin Number
1
P_CHG_IN
Pin Number
1
P_CHASSIS
Pin Number
1
P_LTE_RESET
Pin Number
1
C_HUB_XTALO
Capacitance
18pF
C_LTE_OUT_1
Capacitance
22uF
C_HUB_VDD33_1
Capacitance
100 nF
C_GNSS_BULK
Capacitance
10uF
C_HUB_BUCK_OUT1
Capacitance
22uF
C_DC_IN_HF
Capacitance
100nF
C_LTE_EM05_BULK
Capacitance
220uF
C_POE_OR_VCAP
Capacitance
100nF
C_5V_OUT2
Capacitance
47uF
C_GNSS_BUCK_OUT2
Capacitance
22uF
C_5V_BOOT
Capacitance
100nF
C_LTE_VCC
Capacitance
1uF
C_HUB_VDDA33_2
Capacitance
100 nF
C_HUB_BUCK_VCC
Capacitance
1uF
C_HUB_BUCK_OUT2
Capacitance
22uF
C_5V_OUT1
Capacitance
47uF
C_CM4_HF
Capacitance
0.1uF
C_LTE_BULK
Capacitance
100uF
C_CHG_DRV
Capacitance
4.7uF
C_LTE_EM05_10P
Capacitance
10pF
C_GNSS_BUCK_IN
Capacitance
10uF
C_CHG_BAT_CONV_BULK
Capacitance
100uF
C_GNSS_BUCK_HF
Capacitance
220nF
C_LTE_EM05_1U
Capacitance
1uF
C_GNSS_BUCK_VCC
Capacitance
1uF
C_HUB_VDD2
Capacitance
0.1uF
C_CHG_SYS_BULK
Capacitance
100uF
C_LTE_BUCK_HF
Capacitance
220nF
C_LTE_OUT_2
Capacitance
22uF
C_HUB_RESET
Capacitance
100nF
C_5V_HF
Capacitance
220nF
C_HUB_VDDA_BULK
Capacitance
1 µF
C_CHG_VAC
Capacitance
1uF
C_AUX_IN
Capacitance
1uF
C_CHG_SRN_CM
Capacitance
0.1uF
C_HUB_BUCK_BOOT
Capacitance
100nF
C_5V_IN
Capacitance
10uF
C_CHG_AC_DIFF
Capacitance
0.47uF
C_LTE_EM05_33P
Capacitance
33pF
C_CHG_ACN_CM
Capacitance
0.1uF
C_CHG_BAT_HF
Capacitance
2.2uF
C_HUB_CRFILT
Capacitance
0.1uF
C_CHG_ACP_CM
Capacitance
0.1uF
C_HUB_PLLFILT
Capacitance
0.1uF
C_HUB_BUCK_HF
Capacitance
220nF
C_HUB_VDD33_2
Capacitance
100 nF
C_CM4_BULK
Capacitance
10uF
C_AUX_OUT
Capacitance
1uF
C_DC_IN_BULK
Capacitance
47uF
C_CHG_SYS_HF
Capacitance
2.2uF
C_CHG_SRP_CM
Capacitance
0.1uF
C_CHG_BTST1
Capacitance
470nF
C_POE_OUT_HF
Capacitance
100nF
C_SIM_VCC
Capacitance
0.1uF
C_HUB_VDDA33_1
Capacitance
100 nF
C_LTE_BOOT
Capacitance
100nF
C_5V_FF
Capacitance
33pF
C_CHG_BAT_DIFF
Capacitance
0.47uF
C_GNSS_BUCK_OUT1
Capacitance
22uF
C_DC_OR_VCAP
Capacitance
100nF
C_CHG_BAT_PACK_BULK
Capacitance
100uF
C_HUB_XTALI
Capacitance
18pF
C_HUB_VDD1
Capacitance
0.1uF
C_LTE_HF
Capacitance
0.1uF
C_GNSS_BUCK_BOOT
Capacitance
100nF
C_CHG_REGN
Capacitance
4.7uF
C_HUB_VDDA33_3
Capacitance
100 nF
C_HUB_VDDA33_4
Capacitance
100 nF
C_HUB_BUCK_IN
Capacitance
10uF
C_CHG_BTST2
Capacitance
470nF
C_LTE_BUCK_IN
Capacitance
10uF
R_CHG_ACN_FILT
Resistance
10 Ω
R_HUB_OCS_PU
Resistance
10kΩ
R_HUB_RBIAS
Resistance
12kΩ
R_CHG_FSW
Resistance
80kΩ
R_GNSS_EN_PD
Resistance
100kΩ
R_HUB_CFG1_PD
Resistance
100kΩ
R_CHG_TS_BOT
Resistance
30.31kΩ
R_HUB_P4DIS_P
Resistance
10kΩ
R_CHG_BAT_SNS
Resistance
5mΩ
R_CHG_SRP_FILT
Resistance
10 Ω
R_CHG_SCL_PU
Resistance
10kΩ
R_CHG_PG_PU
Resistance
10kΩ
R_CHG_TS_TOP
Resistance
5.24kΩ
R_CHG_FB_TOP
Resistance
249kΩ
R_CHG_ACP_FILT
Resistance
10 Ω
R_CHG_INT_PU
Resistance
10kΩ
R_LTE_FB_TOP
Resistance
100kΩ
R_CHG_FB_BOT
Resistance
55.6kΩ
R_CHG_AC_SNS
Resistance
2mΩ
R_CHG_CE_PU
Resistance
10kΩ
R_HUB_NONREM1_PU
Resistance
100kΩ
R_LTE_PG_PU
Resistance
100kΩ
R_CHASSIS_BOND
Resistance
1MΩ
R_CHG_ILIM
Resistance
24.9kΩ
R_GNSS_BUCK_FB_BOT
Resistance
43.2kΩ
R_HUB_CFG0_PD
Resistance
100kΩ
R_GNSS_BUCK_FB_TOP
Resistance
100kΩ
R_LTE_FB_BOT
Resistance
43.2kΩ
R_CHG_SRN_FILT
Resistance
10 Ω
R_5V_FB_BOT
Resistance
19.1kΩ
R_CHG_ICHG
Resistance
49.9kΩ
R_HUB_RESET_PU
Resistance
10kΩ
R_HUB_BUCK_FB_BOT
Resistance
43.2kΩ
R_HUB_NONREM0_PD
Resistance
100kΩ
R_LTE_RESET_PU
Resistance
100kΩ
R_SIM_DET_FIX
Resistance
100kΩ
R_LTE_EN_PD
Resistance
100kΩ
R_HUB_BUCK_FB_TOP
Resistance
100kΩ
R_5V_FB_TOP
Resistance
100kΩ
R_HUB_P4DIS_M
Resistance
10kΩ
R_LTE_WDIS_PU
Resistance
100kΩ
R_MOSAIC_RESET_PU
Resistance
100kΩ
R_CHG_SDA_PU
Resistance
10kΩ
U_GNSS_BUCK
U_HUB_BUCK
U_LTE_BUCK
U_5V_BUCK
U_CM4
Q_CHG_BATFET_SYS
Q_DC_OR
Q_POE_OR
L_5V_BUCK
Inductance
4.7uH
C_POE_Y_NEG
Capacitance
4700pF
D_ESD_ETH_B
D_ESD_ETH_A
C_POE_Y_POS
Capacitance
4700pF
J_M2_LTE
L_CHG_POWER
Inductance
10µH
L_LTE_BUCK_REAL
Inductance
2.2uH
D_POE_IN_TVS
Q_CHG_BOOST_HS
Q_CHG_BUCK_HS
Q_CHG_BOOST_LS
Q_CHG_BATFET_BAT
L_HUB_BUCK
Inductance
2.2uH
Q_CHG_BUCK_LS
L_GNSS_BUCK
Inductance
2.2uH
Q_CHG_ACFET_SYS
Q_CHG_ACFET_IN
F_BAT
J_ETH
C_CHASSIS_BOND
Capacitance
1000 pF
D_CHG_ACDRV_Z
D_ESD_SIM
U_USBHUB
J_BAT
J_SIM
Power Source Research and Defaults
Date: 2026-07-20 Project: CM4 PoE UPS RTK Carrier
Executive recommendation
Keep the Power Architecture Hard Gate active, but do not block non-power schematic development while final battery and power-path details are gathered.
Recommended defaults for the next implementation pass:
  1. BQ25750 design authority: use the latest official TI BQ25750 datasheet, BQ25750EVM User Guide Rev. B / SLUUCY7B, TI BQ25750 schematic/layout checklist, and TI E2E design-file threads as references. The editable EVM CAD files are useful but not mandatory.
  2. PoE+ default: use a 12 V isolated IEEE 802.3at PoE+ module as the default intermediate rail.
    • Preferred external BOM target: Silvertel Ag5412 if we want the newer Ag5400 family.
    • Flux-library-available implementation part: Silvertel AG5300, 12 V / 2.5 A isolated PoE module, part UID dde9bf77-ffc7-4620-972a-a0a2d31f62fc.
    • 24 V option: Silvertel Ag5424 if lower secondary-side current is worth the higher downstream voltage stress.
  3. LTE default: give the Quectel EM05 its own 3.3 V / 3 A supply branch with local bulk capacitance and controlled power sequencing.
  4. GNSS default: keep Mosaic/mini PCIe on a separate clean 3.3 V rail with filtering/load control isolated from LTE burst current.
  5. Charging default: configure BQ25750 for 2S Li-ion / 8.4 V regulation, but keep charge current and compensation values provisional until the exact battery pack and TI-derived calculations are complete.
TI BQ25750 sources found

Table


SourceStatusHow to use
TI BQ25750 product pageFoundPrimary source for datasheet, product collateral, EVM, and design resources.
BQ25750EVM User Guide, SLUUCY7B, Rev. B, revised May 2025FoundAuthoritative EVM schematic, BOM, layout plots, operating limits, setup, and caveats.
TI E2E FAQ: BQ25750 Schematic and Layout ChecklistFoundFormal checklist before schematic/layout release. If checklist conflicts with datasheet, datasheet wins.
TI E2E design-file thread: BQ25750_EVM_Altium_Design_Files.zipFoundUseful optional source if accessible. Not a blocker.
TI E2E ASCII design-file threadFoundOptional alternative CAD reference if native files are difficult to import.
Important BQ25750EVM caveats
  • EVM is a lab evaluation board, not production hardware.
  • EVM limits: 55 V max input, 30 V max output, 10 A max charge current.
  • EVM defaults include 8 A input current, 10 A output current, and 250 kHz switching frequency.
  • EVM has no installed fuse and is not a complete product safety design.
  • The carrier design must independently validate FETs, inductor, current sense, compensation, thermal performance, clearances, fusing, reverse-current blocking, and battery safety.
TI checklist items that must be implemented/verified

Table


Circuit itemRequirement / extracted guidance
Buck/boost FETsFour N-channel switching MOSFETs Q1-Q4 required. Gate drive resistors typically 0 ohm; no gate-source pulldowns unless TI says otherwise.
BootstrapSchottky bootstrap diodes; 100 nF bootstrap caps close to IC; DRV_SUP 4.7 uF close to IC.
Input protection FETsOptional back-to-back input N-FETs; gate-source zener around 15 V if used.
Battery FETsBATDRV drives N-channel battery FETs; gate-drive limiting resistor and turn-on cap per checklist/EVM.
InductorRequired; checklist gives 2.2 uH min, 10 uH typical, 15 uH max range. Must be recalculated for this 2S UPS load/thermal case.
Input current senseRAC optional, 0-5 mΩ. If not used, short ACP/ACN to VAC. For PoE/DC input limiting, RAC is likely useful.
Battery current senseRBAT/SRP-SRN sense resistor is 5 mΩ fixed; different value not recommended by TI checklist. Kelvin route.
Input capacitanceBulk input capacitance 80 uF min / 160 uF typ, mix ceramic + electrolytic.
Output capacitanceBulk output capacitance 80 uF min / 160 uF typ, mix ceramic + electrolytic.
TS thermistorReal 10 k NTC such as 103AT-2 style network from REGN to TS to PGND; select divider values from BQ25750 datasheet JEITA section.
LayoutMinimize buck/boost switching loops; Kelvin sense resistors; keep sense traces away from switch nodes; analog ground plane tied to PGND under exposed pad; lowest-value bypass capacitors closest to IC.
Quectel EM05 hardware guide findings
Public source found: Quectel_EM05_Hardware_Design_V1.2-2.pdf, dated 2020-01-07. Official Quectel EM05 product page also lists EM05-G/EM05-E variant guides, with some downloads login-restricted.
EM05 power requirements

Table


ItemRequirement
VCC operating range3.135 V to 4.4 V
Typical VCC3.3 V
VCC pinsM.2 pins 2, 4, 70, 72, 74
Ground pins3, 5, 11, 27, 33, 39, 45, 51, 57, 71, 73
Supply current capabilityAt least 2.0 A; reference supply supports 3.0 A
VCC droop warningMust not fall below 3.135 V during burst transmission
Local VCC capacitance220 uF low-ESR bulk plus 1 uF, 100 nF, 33 pF, 10 pF close to VCC pins
VCC TVSLow clamp TVS; Quectel suggests VRWM 4.7 V class
VCC routingWide trace, about >= 2 mm where practical
Implementation implication: 3V3_LTE must be a dedicated regulator/load-switch branch sized for 3 A transient margin, not a shared logic rail.
EM05 USB requirements

Table


ItemRequirement
InterfaceUSB 2.0 device/slave
SpeedHigh-speed 480 Mbps
DP/DM impedance90 ohm differential
ESDLow-capacitance USB ESD, typically **=30 ms. Boot to active can take >=12 s.
RESET#Pin 67; active low; pulse low 150-460 ms; no large capacitance on reset. Before forced shutdown, Quectel recommends pulling RESET# low around 100 ms to avoid flash damage.
W_DISABLE1#Pin 8; active low RF disable; hardware control disabled by firmware by default and can be enabled using AT+QCFG="airplanecontrol".
PoE+ module options

Table


CandidateOutputPowerLibrary statusRecommendation
Silvertel Ag541212 V / 2.5 A30 WNot found in Flux libraryPreferred external BOM target if using Ag5400 family; request/add symbol if selected.
Silvertel Ag542424 V / 1.25 A30 WNot found in Flux libraryGood alternate if 24 V intermediate bus is desired.
Silvertel AG530012 V / 2.5 A30 W classFound in Flux libraryBest immediate implementation default because symbol exists.
Silvertel AG5712-LPB12 V / 2.5 A30 WNot found in Flux libraryLow-profile alternate; evaluate if height/area matters.
PoweredEthernet PEM321212 V~24-30 W peak depending datasheetNot found in Flux librarySecondary-source candidate; verify continuous output before use.
Silvertel Ag59812-LPB / Ag59824-LPB12 V / 24 V802.3bt high-power classNot searched in library this passUpgrade path if PoE+ power budget is too tight.
Ag5400 family extracted constraints
  • IEEE 802.3at Type 2 Class 4 PD; backward compatible with 802.3af and usable in 802.3bt environments.
  • In compliant PoE+, PSE output may be 30 W but the PD can rely on about 25.5 W available after cable loss before module/downstream losses.
  • Ag5412 output: 12 V, 2.5 A, 30 W continuous.
  • Ag5424 output: 24 V, 1.25 A, 30 W continuous.
  • Isolation: 1500 Vdc input-to-output.
  • Efficiency: Ag5412 peak about 93.3%.
  • Operating temperature: -40°C to +85°C, but enclosure derating still required.
  • Output cap required close to output pins. Ag5412 recommendation: 220 uF minimum, 470 uF typical, 1000 uF max, low ESR suitable for low temperature.
  • If an auxiliary/external supply can drive the module output, Silvertel requires a blocking diode or equivalent to prevent output backfeed into the PoE module.
Default architecture after research

Text


RJ45 / Ethernet magnetics / PoE input -> isolated 12 V PoE+ module, default AG5300 in Flux or Ag5412 external BOM target -> reverse-current blocking / ideal-diode OR with external DC input -> BQ25750 input / direct power-path / 2S charger, provisional until TI checklist complete -> downstream rails: 5V_CM dedicated CM4 regulator 3V3_LTE dedicated 3 A LTE regulator/load switch 3V3_GNSS clean GNSS regulator/filter/load switch 3V3_HUB USB hub/logic rail 3V3_AUX low-current control/peripheral rail
Remaining documents / unresolved decisions before production-ready schematic
Required documents/datasheets
  1. Exact Ansmann 2S Li-ion pack datasheet: capacity, max charge current, discharge current, protection status, NTC value/B-constant, connector pinout, certifications.
  2. Latest official BQ25750 datasheet revision used for final calculations.
  3. TI BQ25750EVM SLUUCY7B and BQ25750 schematic/layout checklist retained as release-review references.
  4. Exact Quectel EM05 variant hardware guide: EM05-E, EM05-G, or other regional SKU; verify against the public general guide.
  5. Exact Mosaic-X5 / simpleRTK3B mini PCIe electrical and mechanical documentation.
  6. Exact PoE module datasheet for chosen module: AG5300 vs Ag5412 vs Ag5424.
  7. External DC connector and source specification: nominal/min/max voltage, current limit, surge/transient environment, polarity expectations.
  8. Ethernet magnetics / RJ45 / surge-protection part datasheets.
  9. USB ESD and SIM ESD protection datasheets.
  10. RF connector and antenna/cable datasheets.
  11. Enclosure/chassis grounding and mounting constraints.
Unresolved design decisions
  1. Choose PoE implementation part for schematic: AG5300 now vs create/request Ag5412.
  2. Choose intermediate power bus: default 12 V, alternate 24 V.
  3. Decide whether rev A supports PoE+ only with charge throttling or adds 802.3bt option for higher charging headroom.
  4. Set external DC input nominal/range and whether it should override PoE, share with PoE, or be priority-selected.
  5. Define BQ25750 operating mode: standalone resistor programming only, I2C-supervised by CM4, or supervisor MCU controlled.
  6. Define battery charge current limit under PoE+ and under external DC.
  7. Select NTC topology and connector pinout once battery pack is known.
  8. Decide whether to include a fuel gauge in rev A.
  9. Decide LTE modem exact region/variant and whether eSIM is required.
  10. Decide whether LTE and GNSS supplies need independent load switches under watchdog/supervisor control.
  11. Define chassis/earth strategy for PoE isolation, Ethernet shield, USB shields, RF shields, and TVS returns.
  12. Define manufacturing target footprints and JLCPCB availability for the chosen PoE module and protection parts.
Immediate next schematic actions enabled by this research
  1. Implement PoE+ input using AG5300 from the Flux library unless user chooses to wait for Ag5412 symbol creation.
  2. Add external DC input block and ideal-diode/reverse-current blocking so PoE and DC cannot backfeed each other.
  3. Add dedicated 3V3_LTE regulator/load switch with EM05-required bulk/MLCC/TVS/passive footprints.
  4. Add dedicated 3V3_GNSS clean rail regulator/filter/load switch.
  5. Leave BQ25750 power stage marked provisional until final component values are checked against TI datasheet/checklist and battery data.