Project Redesign Brief


Because the previous full-board placement oscillated, I’m going to use deterministic moves for the main crowded blocks first, then run the placement agent only to clean passives around those anchors.
The anchor move separated the big zones and fixed some previous placement problems, but many passives now need cleanup around those anchors. I’m handing only the overlap cleanup to the placement engine and allowing small passives on the bottom.
The cleanup pass still could not converge; the overlap set is oscillating. I’m doing one final broader fresh placement with looser grouping priorities: first objective is simply no physical overlaps and all parts inside the board, still with no routing.
I have rearrange the the board this is the finaly position of the cm4, mosiac and 4g modem - correct the io board mounting holes to match the offical io board hole locations as they are currently incorrect, also add/correct the fixings and mounts and holes for the m.2, cm4 and mpcie units to suit the quectel em05 and the mosiac, here are the data sheets.
I’ll preserve your manually placed CM4/Mosaic/4G positions, then correct only mechanical items: official CM4 IO mounting holes, CM4 mounting/fixing holes, and M.2/mPCIe standoff holes from the provided datasheets. I’ll source/inspect the official geometry before mutating holes.

U_DC_OR
D_ESD_USB_SERVICE
Y_HUB_24M
Resistance
60 ohms
D_ESD_USB_LTE
J_MPCIE_GNSS
U_CHG
D_ESD_USB_MOSAIC
U_AUX_LDO
U_POE_OR
PS_POE
D_POE_12V_TVS
R_CHG_ACN_FILT
Resistance
10 Ω
R_HUB_OCS_PU
Resistance
10kΩ
R_HUB_RBIAS
Resistance
12kΩ
R_CHG_FSW
Resistance
80kΩ
R_GNSS_EN_PD
Resistance
100kΩ
R_HUB_CFG1_PD
Resistance
100kΩ
R_CHG_TS_BOT
Resistance
30.31kΩ
R_HUB_P4DIS_P
Resistance
10kΩ
R_CHG_BAT_SNS
Resistance
5mΩ
R_CHG_SRP_FILT
Resistance
10 Ω
R_CHG_SCL_PU
Resistance
10kΩ
R_CHG_PG_PU
Resistance
10kΩ
R_CHG_TS_TOP
Resistance
5.24kΩ
R_CHG_FB_TOP
Resistance
249kΩ
R_CHG_ACP_FILT
Resistance
10 Ω
R_CHG_INT_PU
Resistance
10kΩ
R_LTE_FB_TOP
Resistance
100kΩ
R_CHG_FB_BOT
Resistance
55.6kΩ
R_CHG_AC_SNS
Resistance
2mΩ
R_CHG_CE_PU
Resistance
10kΩ
R_HUB_NONREM1_PU
Resistance
100kΩ
R_LTE_PG_PU
Resistance
100kΩ
R_CHASSIS_BOND
Resistance
1MΩ
R_CHG_ILIM
Resistance
24.9kΩ
R_GNSS_BUCK_FB_BOT
Resistance
43.2kΩ
R_HUB_CFG0_PD
Resistance
100kΩ
R_GNSS_BUCK_FB_TOP
Resistance
100kΩ
R_LTE_FB_BOT
Resistance
43.2kΩ
D_DC_IN_TVS
R_CHG_SRN_FILT
Resistance
10 Ω
R_5V_FB_BOT
Resistance
19.1kΩ
R_CHG_ICHG
Resistance
49.9kΩ
R_HUB_RESET_PU
Resistance
10kΩ
R_HUB_BUCK_FB_BOT
Resistance
43.2kΩ
R_HUB_NONREM0_PD
Resistance
100kΩ
R_LTE_RESET_PU
Resistance
100kΩ
R_SIM_DET_FIX
Resistance
100kΩ
R_LTE_EN_PD
Resistance
100kΩ
R_HUB_BUCK_FB_TOP
Resistance
100kΩ
R_5V_FB_TOP
Resistance
100kΩ
R_HUB_P4DIS_M
Resistance
10kΩ
R_LTE_WDIS_PU
Resistance
100kΩ
R_MOSAIC_RESET_PU
Resistance
100kΩ
R_CHG_SDA_PU
Resistance
10kΩ
C_HUB_XTALO
Capacitance
18pF
C_LTE_OUT_1
Capacitance
22uF
C_HUB_VDD33_1
Capacitance
100 nF
C_GNSS_BULK
Capacitance
10uF
C_HUB_BUCK_OUT1
Capacitance
22uF
C_DC_IN_HF
Capacitance
100nF
C_LTE_EM05_BULK
Capacitance
220uF
C_POE_OR_VCAP
Capacitance
100nF
C_5V_OUT2
Capacitance
47uF
C_GNSS_BUCK_OUT2
Capacitance
22uF
C_5V_BOOT
Capacitance
100nF
C_LTE_VCC
Capacitance
1uF
C_HUB_VDDA33_2
Capacitance
100 nF
C_HUB_BUCK_VCC
Capacitance
1uF
C_HUB_BUCK_OUT2
Capacitance
22uF
C_5V_OUT1
Capacitance
47uF
C_CM4_HF
Capacitance
0.1uF
C_LTE_BULK
Capacitance
100uF
C_CHG_DRV
Capacitance
4.7uF
C_LTE_EM05_10P
Capacitance
10pF
C_GNSS_BUCK_IN
Capacitance
10uF
C_CHG_BAT_CONV_BULK
Capacitance
100uF
C_GNSS_BUCK_HF
Capacitance
220nF
C_LTE_EM05_1U
Capacitance
1uF
C_GNSS_BUCK_VCC
Capacitance
1uF
C_HUB_VDD2
Capacitance
0.1uF
C_CHG_SYS_BULK
Capacitance
100uF
C_LTE_BUCK_HF
Capacitance
220nF
C_LTE_OUT_2
Capacitance
22uF
C_HUB_RESET
Capacitance
100nF
C_5V_HF
Capacitance
220nF
C_HUB_VDDA_BULK
Capacitance
1 µF
C_CHG_VAC
Capacitance
1uF
C_AUX_IN
Capacitance
1uF
C_CHG_SRN_CM
Capacitance
0.1uF
C_HUB_BUCK_BOOT
Capacitance
100nF
C_5V_IN
Capacitance
10uF
C_CHG_AC_DIFF
Capacitance
0.47uF
C_LTE_EM05_33P
Capacitance
33pF
C_CHG_ACN_CM
Capacitance
0.1uF
C_CHG_BAT_HF
Capacitance
2.2uF
C_HUB_CRFILT
Capacitance
0.1uF
C_CHG_ACP_CM
Capacitance
0.1uF
C_HUB_PLLFILT
Capacitance
0.1uF
C_HUB_BUCK_HF
Capacitance
220nF
C_HUB_VDD33_2
Capacitance
100 nF
C_CM4_BULK
Capacitance
10uF
C_AUX_OUT
Capacitance
1uF
C_DC_IN_BULK
Capacitance
47uF
C_CHG_SYS_HF
Capacitance
2.2uF
C_CHG_SRP_CM
Capacitance
0.1uF
C_CHG_BTST1
Capacitance
470nF
C_POE_OUT_HF
Capacitance
100nF
C_SIM_VCC
Capacitance
0.1uF
C_HUB_VDDA33_1
Capacitance
100 nF
C_LTE_BOOT
Capacitance
100nF
C_5V_FF
Capacitance
33pF
C_CHG_BAT_DIFF
Capacitance
0.47uF
C_GNSS_BUCK_OUT1
Capacitance
22uF
C_DC_OR_VCAP
Capacitance
100nF
C_CHG_BAT_PACK_BULK
Capacitance
100uF
C_HUB_XTALI
Capacitance
18pF
C_HUB_VDD1
Capacitance
0.1uF
C_LTE_HF
Capacitance
0.1uF
C_GNSS_BUCK_BOOT
Capacitance
100nF
C_CHG_REGN
Capacitance
4.7uF
C_HUB_VDDA33_3
Capacitance
100 nF
C_HUB_VDDA33_4
Capacitance
100 nF
C_HUB_BUCK_IN
Capacitance
10uF
C_CHG_BTST2
Capacitance
470nF
C_LTE_BUCK_IN
Capacitance
10uF
P_PWR_GOOD
Pin Number
1
P_CHG_INT
Pin Number
1
P_ETH_TRD0_P
Pin Number
1
P_SIM_RST
Pin Number
1
P_GND
Pin Number
1
P_ETH_TRD3_N
Pin Number
1
P_SIM_CLK
Pin Number
1
P_LTE_USB_DP
Pin Number
1
P_ETH_TRD1_N
Pin Number
1
P_ETH_TRD1_P
Pin Number
1
P_ETH_TRD3_P
Pin Number
1
P_SIM_DATA
Pin Number
1
P_LTE_W_DISABLE
Pin Number
1
P_CHG_EN
Pin Number
1
P_SAFE_SHUTDOWN
Pin Number
1
P_FG_INT
Pin Number
1
P_BAT_NTC
Pin Number
1
P_MOSAIC_PWR_EN
Pin Number
1
P_SERVICE_USB_DP
Pin Number
1
P_LTE_USB_DM
Pin Number
1
P_ETH_TRD2_N
Pin Number
1
P_WD_HEARTBEAT
Pin Number
1
P_SIM_VCC
Pin Number
1
P_ETH_TRD2_P
Pin Number
1
P_I2C_SDA
Pin Number
1
P_MOSAIC_USB_DP
Pin Number
1
P_SIM_DET
Pin Number
1
P_CM_USB_DM
Pin Number
1
P_CM_RUN_RESET
Pin Number
1
P_I2C_SCL
Pin Number
1
P_5V_CM
Pin Number
1
P_3V3_AUX
Pin Number
1
P_BAT_2S
Pin Number
1
P_HUB_RESET
Pin Number
1
P_3V3_HUB
Pin Number
1
P_MOSAIC_USB_DM
Pin Number
1
P_MOSAIC_RESET
Pin Number
1
P_HUB_CLK
Pin Number
1
P_SYS_BUS
Pin Number
1
P_POE_RAW
Pin Number
1
P_3V3_GNSS
Pin Number
1
P_CM_USB_DP
Pin Number
1
P_3V3_LTE
Pin Number
1
P_LTE_PWR_EN
Pin Number
1
P_SERVICE_USB_DM
Pin Number
1
P_DC_RAW
Pin Number
1
P_ETH_TRD0_N
Pin Number
1
P_CHG_IN
Pin Number
1
P_CHASSIS
Pin Number
1
P_LTE_RESET
Pin Number
1
U_5V_BUCK
U_GNSS_BUCK
D_CHG_ACDRV_Z
J_SIM
U_HUB_BUCK
U_LTE_BUCK
C_POE_Y_NEG
Capacitance
4700pF
J_ETH
C_CHASSIS_BOND
Capacitance
1000 pF
D_ESD_SIM
U_USBHUB
J_BAT
C_POE_Y_POS
Capacitance
4700pF
Q_CHG_BOOST_HS
Q_CHG_BUCK_HS
L_5V_BUCK
Inductance
4.7uH
D_ESD_ETH_B
Q_CHG_BOOST_LS
Q_CHG_BATFET_BAT
F_BAT
D_ESD_ETH_A
Q_CHG_BUCK_LS
Q_CHG_ACFET_SYS
Q_CHG_ACFET_IN
Q_CHG_BATFET_SYS
J_M2_LTE
L_CHG_POWER
Inductance
10µH
L_LTE_BUCK_REAL
Inductance
2.2uH
D_POE_IN_TVS
Q_DC_OR
L_HUB_BUCK
Inductance
2.2uH
L_GNSS_BUCK
Inductance
2.2uH
Q_POE_OR
U_CM4
BR_POE_A
FB_POE_IN_N
C_POE_OUT_BULK_REAL
D_LTE_3V3_TVS
J_DC_IN
BR_POE_B
FB_POE_IN_P
Power Architecture Hard Gate
Status: Active requirement before further optimisation.
User Requirement
The power system must be made robust and production-intent before continuing. Reliability is prioritised over component count or BOM cost.
Hard Requirements
  1. Rework the entire BQ25750 section from official Texas Instruments source material only.
    • Use TI BQ25750 datasheet, EVM/reference design, hardware checklist, and preferably TI design files.
    • Verify MOSFETs, inductor, current-sense resistors, compensation/reference networks, bootstrap components, input/output capacitors, and all surrounding circuitry.
    • Do not use an AI-generated topology as the final implementation.
  2. Configure the charger for the actual battery target.
    • 2S2P Li-ion.
    • 7.4V nominal.
    • 8.4V maximum charge voltage.
    • Approximately 5.2Ah capacity.
    • Correct charge voltage, charge current, input-current limiting, and protection settings required.
  3. Add a real external 10k NTC battery thermistor connection.
    • BQ25750 TS must monitor the battery pack in hardware.
    • Charging must suspend outside the safe temperature range.
    • TS must not be simulated by fixed resistors.
  4. Implement proper PoE/DC power-path management.
    • PoE must not backfeed DC input.
    • DC must not backfeed PoE module.
    • Source selection must be stable and reliable.
    • System must transition between PoE, DC, and battery without interruption.
  5. Size LTE modem power properly from the Quectel EM05 hardware guide.
    • Regulator, bulk capacitance, and decoupling must be based on Quectel data, not estimates.
  6. Keep Mosaic/GNSS on its own clean power rail.
    • Must be independent from LTE supply.
    • Must include local filtering and decoupling.
  7. Add industrial protection.
    • Ethernet surge protection.
    • USB ESD protection.
    • TVS devices on external interfaces.
    • Proper chassis/shield grounding strategy.
  8. Ensure all rails have manufacturer-recommended local decoupling and bulk capacitance.
  9. Produce a complete power tree:
    • PoE -> power management.
    • DC -> power management.
    • Battery -> BQ25750.
    • BQ25750 -> 5V system rail.
    • 5V -> Compute Module, USB hub, and power converters.
    • Separate regulated supplies for Mosaic and LTE modem.
  10. Run full ERC and verify the complete power architecture before continuing.
Current Schematic Reality Check
  • LTE is currently on a separate named net, 3V3_LTE, with provisional 100uF + 0.1uF local capacitance, but no real regulator/load switch has been implemented.
  • Mosaic/GNSS is currently on a separate named net, 3V3_GNSS, with provisional local capacitance, but no real clean regulator/filter/load switch has been implemented.
  • Shared 3.3V rails are separated by net names, but physical rail generation is incomplete.
  • BQ25750 power-stage pins are still open and must be implemented from TI reference material.
  • TS currently goes to BAT_NTC marker only; no real external NTC connector/network exists yet.
  • PoE/DC OR-ing, reverse-current blocking, and input protection are not yet implemented.
  • Industrial protection is not yet implemented.
  • EM05 mapping is provisional and still requires exact Quectel guide verification.
Datasheet Facts Extracted So Far
  • BQ25750 FB reference default: 1.536V.
  • TI recommends RTOP = 249k for FB divider examples.
  • For 8.4V target, calculated FB bottom resistor is approximately 55.75k before selecting an exact 0.1% value.
  • BQ25750 battery sense resistor between SRP/SRN is fixed/recommended at 5 milliohm.
  • BQ25750 input sense resistor is typically 2 milliohm; higher values such as 5 milliohm may improve lower-current resolution.
  • BQ25750 REGN and DRV_SUP need 4.7uF ceramic capacitors to PGND; REGN can supply DRV_SUP depending on implementation.
  • BQ25750 TS network is designed for an external 103AT-2 style 10k NTC with resistor network; example values for 0C to 60C range are RT1 = 5.24k and RT2 = 30.31k per datasheet extraction.
  • BQ25750 power stage requires external MOSFETs, bootstrap capacitors from BTST1-SW1 and BTST2-SW2, inductor between SW1 and SW2, Kelvin current-sense routing, and TI layout guidance.
Blockers Before Production-Ready Power Implementation
  1. Exact Ansmann 2S2P battery pack datasheet/part number, charge-current rating, connector pinout, NTC type/curve, and protection/BMS details.
  2. TI BQ25750EVM design files or official reference schematic/checklist accepted as source of truth.
  3. Exact PoE+ PD module/controller selection and output voltage/current.
  4. External DC connector and confirmed voltage/current/surge environment.
  5. Exact Quectel EM05 variant and hardware design guide revision.
  6. ArduSimple simpleRTK3B / Mosaic-X5 power and antenna-bias documentation.
  7. Enclosure, antenna connector, cable-entry, and chassis/shield grounding constraints.
Next Implementation Order
  1. Freeze source documents and component choices for BQ25750, battery, PoE, DC input, EM05, and Mosaic.
  2. Implement BQ25750 reference power stage and current/voltage/temperature sensing.
  3. Implement PoE/DC source OR-ing and reverse-current blocking.
  4. Implement 5V system, 3V3_LTE, 3V3_GNSS, 3V3_HUB, and auxiliary rails.
  5. Add industrial ESD/surge/TVS/chassis protection.
  6. Run ERC and document remaining issues.
  • User Requirement

  • Hard Requirements

  • Current Schematic Reality Check

  • Datasheet Facts Extracted So Far

  • Blockers Before Production-Ready Power Implementation

  • Next Implementation Order