Phase 1 Schematic Plan
Status: Execution plan for the first electrical skeleton.
Goal
Create a datasheet-backed architecture-validation schematic that proves compute, USB topology, power-path concept, reset/watchdog strategy, and major external interfaces before detailed layout or manufacturing claims.
Functional Sheets / Blocks
1. Top-Level Rails and Signals
- Named rails: POE_RAW, DC_RAW, VIN_PROT, CHG_IN, BAT_2S, SYS_BUS, 5V_CM, 5V_GNSS, 3V3_LTE, 3V3_AUX, 3V3_HUB, 1V2_HUB if required, GND, CHASSIS.
- Source priority and current-limit notes.
- Test-point list for all rails and control signals.
2. CM4 Core Interface
- CM4 connectors as committed Rev A target.
- 5V input and decoupling.
- RUN/reset/safe-shutdown path.
- USB 2.0 upstream to hub.
- Ethernet signals to Ethernet/PoE block.
- I2C/SMBus to BQ25750 and fuel gauge.
- GPIOs reserved for:
- LTE reset.
- LTE load-switch enable.
- Mosaic reset.
- Mosaic load-switch enable.
- Watchdog heartbeat.
- Charger interrupt/status.
- Fuel gauge interrupt/status.
- Power-good/status inputs.
- Safe shutdown/reboot control.
3. USB2514Bi Hub
- Upstream USB 2.0 to CM4.
- Downstream port allocation:
- Port 1: Mosaic/simpleRTK3B mini PCIe USB.
- Port 2: Quectel EM05 M.2 USB.
- Port 3: internal service USB.
- Port 4: spare/test expansion if useful.
- Hub reset, clock/crystal, configuration straps/EEPROM, decoupling, power-good, and overcurrent/power-enable policy.
4. Mosaic/simpleRTK3B Mini PCIe Interface
- Mini PCIe connector wired for USB-only module operation.
- Required power pins and clean GNSS power branch.
- Reset line and optional load-switch footprint or 0 ohm bypass.
- Presence/status pins only if required by module documentation.
- No-connect treatment for unused PCIe/SIM pins after checking ArduSimple/Septentrio docs.
- RF handling note: either module antenna connector or carrier RF connector strategy must be confirmed.
5. Quectel EM05 M.2 LTE Interface
- M.2 B-key connector.
- USB 2.0 D+/D- from hub.
- 3.3V LTE rail, local bulk capacitance placeholder, and enable/power switching.
- Reset/control pins per Quectel hardware guide.
- SIM interface nets.
- LTE main and diversity RF connector placeholders.
- Required pull-ups/pull-downs and no-connect handling from Quectel docs.
6. Nano SIM and ESD
- Nano SIM socket.
- SIM_VCC, SIM_CLK, SIM_RST, SIM_DATA, optional card detect.
- SIM ESD protection placed at connector in layout.
- Series/filter components only if recommended by Quectel/SIM guidance.
7. PoE, DC Input, and BQ25750 Power Path
- Integrated PoE+ PD module or placeholder selected after sourcing check.
- Protected 9-36V DC input.
- Source ORing/power mux concept.
- BQ25750 with 2S Li-ion configuration, battery connector, 10k NTC, sense resistor placeholders, SMBus/I2C, INT/status, power-good and fault signals.
- Input-current limit and charge-current policy notes.
8. Regulators and Load Switches
- 5V_CM rail sized from budget.
- 3V3_AUX rail.
- USB hub rails including 1V2 if required.
- 3V3_LTE rail with transient support.
- GNSS/Mosaic clean rail.
- Load-switch footprints or bypass jumpers for LTE and Mosaic.
- Power-good signals routed to CM where useful.
9. Ethernet and PoE Interface
- CM Ethernet pairs to magnetics/RJ45 concept.
- PoE center-tap extraction path.
- Surge/ESD placeholders.
- Chassis/shield grounding strategy placeholder.
- Controlled-impedance notes.
10. Watchdog and Reset Tree
- Independent watchdog supervisor powered from an appropriate always-on rail.
- Heartbeat GPIO from CM.
- Reset output to CM RUN/reset path.
- Manual/service reset or disable provision for debug.
- Separate reset outputs or GPIO-driven reset nets for LTE and Mosaic.
Validation Gates Before Moving to Layout
- All main ICs/connectors exist in the Flux library or are created from datasheets.
- Every active component has datasheet-backed pin wiring and support passives.
- Power budget is updated with actual datasheet values.
- BQ25750 reference design checklist is complete.
- USB topology and port power/reset behavior are documented.
- CM4/CM5 compatibility matrix is updated.
- ERC/design review is clean or remaining warnings are documented.
Instantiation Status
2026-07-20: Phase 1 review skeleton instantiated in the schematic as terminal/net-portal markers rather than final datasheet-backed IC symbols. The concrete Flux library search did not return the real IC/connector symbols in this environment, so the current schematic intentionally captures the named rails, high-speed interfaces, RF paths, SIM signals, reset/control nets, watchdog nets, and charger/fuel-gauge telemetry nets for review.
Current schematic summary after instantiation:
- 59 Terminal markers.
- 58 Net Portal labels plus GND.
- 59 named nets total.
- Power/ground metadata applied to primary rails.
- Controlled-impedance metadata applied to USB 2.0, Gigabit Ethernet, and RF nets.
- ERC currently reports expected single-pin-net warnings because this is a boundary-marker skeleton, not the final wired IC schematic.
2026-07-20 update: Added the first real library symbols requested by the user:
- U_CM4: Raspberry Pi Compute Module 4.
- U_USBHUB: Microchip USB2514B-I/M2 USB hub.
- U_CHG: Texas Instruments BQ25750RRVR charger/power-path controller.
- J_M2_LTE: Amphenol MDT320B03001 M.2 B-key LTE modem socket.
- J_MPCIE_GNSS: TE 1759547-1 mini PCIe socket for Mosaic/simpleRTK3B.
- J_SIM: GCT SIM8060-6-0-14-00-A nano SIM socket.
Initial boundary-level wiring completed:
- CM4 5V, GND, USB 2.0, Ethernet pairs, I2C telemetry, watchdog, reset, LTE/Mosaic control GPIOs.
- USB2514B upstream and downstream USB ports, 3V3 power, reset, clock/config markers, GND.
- BQ25750 I2C, INT, power-good, charge-enable, TS, SYS, VAC, battery sense, and ground pins.
- Mini PCIe USB_D+/D-, 3.3VAUX pins, GND, and PERST# to Mosaic reset.
- M.2 LTE USB_D+/D-, 3V3 LTE pins, GND, W_DISABLE1#, FULL_CARD_POWER_OFF#, RESET#, and SIM pins using provisional Quectel EM05-oriented mapping.
- Nano SIM VCC/RST/CLK/DATA/GND wired; VPP marked no-connect.
Important rail correction: mini PCIe GNSS power is now represented by a clean 3V3_GNSS rail. The earlier 5V_GNSS skeleton marker remains provisional/reserved until the Mosaic/simpleRTK3B power requirements are checked against its documentation.
Current ERC status after this step: expected open warnings remain because many CM4, BQ25750 power-stage, USB hub support, M.2 optional, and mini PCIe optional pins are not yet intentionally no-connected or supported by passives/reference circuits. The next pass should add support passives, no-connect unused pins, and clean schematic placement/routing.
2026-07-20 update: Added first support passives and no-connect cleanup for the six-symbol pass.
Support passives added:
- CM4: 10uF bulk and 0.1uF high-frequency bypass on 5V_CM.
- LTE M.2 socket: provisional 100uF bulk and 0.1uF high-frequency bypass on 3V3_LTE.
- GNSS mini PCIe socket: 10uF bulk on 3V3_GNSS.
- SIM socket: 0.1uF decoupling on SIM_VCC.
- USB2514B: 3V3 decoupling, CRFILT and PLLFILT 0.1uF capacitors, 12k 1% RBIAS, and 10k config/I2C pull-ups.
- BQ25750: VAC, REGN, and DRV_SUP bypass capacitors; 10k pull-ups for SDA, SCL, INT, PG, and CE; provisional ICHG and ILIM_HIZ programming resistors.
No-connect cleanup completed:
- CM4 unused HDMI, DSI, CSI, PCIe, SD, analog, LED, sync, wireless-disable, EEPROM-ID, reserved, and spare GPIO pins were marked no-connect for this headless USB/Ethernet carrier scope.
- USB2514B unused downstream port 4, overcurrent/power-enable placeholders, and optional status pins were marked no-connect for this pass.
- Mini PCIe unused PCIe/SIM/LED/SMBus/COEX/reserved pins were marked no-connect; mechanical pads tied to GND.
- M.2 LTE unused optional pins were marked no-connect; mechanical pads tied to GND.
- BQ25750 optional STAT1, STAT2, and FSW_SYNC were marked no-connect. Power-stage pins are intentionally still open because they require the TI reference-design implementation.
ERC after cleanup:
- Remaining floating-pin warnings are primarily BQ25750 power-stage pins: BTST1/2, HIDRV1/2, LODRV1/2, SW1/2, ACDRV, BATDRV, BATSRC, FB/FBG, ACN/ACP. These should be resolved only when the BQ25750 reference power stage is added.
- Remaining single-pin warnings are expected skeleton/interface markers: BAT_2S, CHASSIS, 5V_GNSS provisional/reserved, DC_OV_FAULT, RF markers, PoE center taps, DC_RAW, 1V2_HUB, and POE_RAW.
- SIM VPP remains reported as a power input by the library symbol even though it is a legacy SIM programming-voltage contact and was marked no-connect. Do not tie it to SIM_VCC unless the Quectel/SIM reference design explicitly requires it.
Next implementation step: replace/augment these terminal markers with the real CM4 connector, USB2514Bi, BQ25750, mini PCIe, M.2 B-key, SIM socket, PoE/DC protection, regulator, load-switch, watchdog, and RF connector symbols after datasheet/library validation.