Project Start Assistance

Thought for 19 mins 43 sec
Thought for 9 sec
1/3 Repair the protected USB copper overlaps and stale breakout geometry

Repair the protected USB copper overlaps and stale breakout geometry

Route all remaining airwires, including ground and VBUS paths

Re-run DRC and verify zero airwires and shorts

Thought for 12 sec
Thought for 5 sec
Awaiting 1 task
"USB-C PCB Fabrication Fix" completed.

flux

I couldn’t retrieve and reconcile the completed repair report before the session ended, so I can’t safely claim that its changes removed the 28 airwires or three USB copper overlaps. No additional result has been verified in this turn; the last confirmed board state remains not fabrication-ready.
Remaining work:
  • Retrieve the completed repair report.
  • Re-run live DRC to verify airwire and overlap counts.
  • Confirm USB breakout recovery, VBUS width, ground-plane continuity, and copper repour.
  • Continue repairs if any violations remain.
Execution stopped because your ACUs ran out.
J

jacobgush

Fix the redundant traces

flux

I’ll run a fresh DRC, delete every copper UID specifically flagged as redundant in one cleanup pass, then re-check to confirm the violations are gone without touching valid routes.

flux

Removed all 12 trace/via nodes flagged as redundant. Fresh DRC confirms zero redundant-trace violations.
The board still has 12 unrelated airwires requiring routing; no valid copper was intentionally removed.
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Schematic

Layout

3D View

Schematic Implementation Notes
Completion status
The complete schematic is implemented with 64 components in eight functional groups. Electrical-rule review is clean with no unresolved errors or warnings. PCB board sizing, placement, stackup, and routing were not modified.
Primary selected parts

Table

FunctionSelected MPN
USB serial / modem controlCH340C
USB 2.0 high-speed switchTS3USB221AQRSERQ1
Source priority / reverse isolationTPS2121RUXT
Downstream eFuse / reverse-current blockingTPS259474LRPWR
DTR inversionSN74LVC1G04DCKR
Host-side 3.3 V LDOTLV75533PDBVR
USB-C receptaclesUJ20-C-H-C-4-SMT-TR
USB data ESDTPD2EUSB30DRTR
CC ESDTPD4E05U06DQAR
VBUS TVSSMAJ5.0A-Q
Implemented behavior
  • J1, J2, and J3 each use independent 5.1 kΩ Rd resistors on CC1 and CC2.
  • J4 uses independent 56 kΩ Rp resistors to OUTPUT_VBUS, advertising USB default current. This remains safe when the board falls back to the current-limited J2 host source.
  • CH340C DTR# and RTS# are active-low modem outputs. DTR# is inverted to active-high VBUS_EN; RTS# directly drives the switch's active-low DATA_EN_N path through a back-power-limiting resistor.
  • Hardware pulls make downstream data disconnected and downstream VBUS off until the control port is powered and software asserts the corresponding modem signals.
  • J3 is connected to TPS2121 IN1 and is preferred over J2 on IN2 using XCOMP priority dividers. The TPS2121 configuration uses 29.8 kΩ at ILM, corresponding to a 3.0 A minimum / 3.5 A typical current-limit range.
  • TPS259474 provides downstream circuit-breaker protection and true reverse-current blocking. A separate two-MOSFET, 100 Ω discharge circuit was added because the TPS259474 does not provide a specified OUT-to-GND active-discharge function.
  • F2 limits J2 fallback current to a 1.1 A hold-class path; F3 is a 4 A hold-class PTC for the 3 A external path. The selected-power and output rails are annotated for 3.5 A and 3.0 A respectively.
  • All exposed USB 2.0 pairs have low-capacitance ESD protection. CC pins have dedicated ESD channels, and each VBUS port has a TVS clamp.
Verification and remaining limitations
  • Electrical-rule checks: clean after classifying connector-fed rails as power nets.
  • All intended IC power pins, decoupling parts, enable pins, timing pins, current-limit pins, Type-C duplicates, shields/grounds, and no-connect pins are explicitly handled.
  • The J4 power path is physically rated for 3 A continuous, but J4 intentionally advertises only USB default current. Advertising 3 A while retaining a low-current J2 fallback would require dynamic Type-C current advertisement or disabling fallback when J3 is absent.
  • The TS3USB221A library part and manufacturer datasheet were selected, but automated citation extraction for its OE truth table and 5 V control-input tolerance failed. Reconfirm those two details manually before release; the schematic uses the standard active-low OE configuration and a 3.3 V switch supply.
  • The TPS259474 ILM is set with 750 Ω so the circuit-breaker threshold remains above a 3 A continuous load; this is deliberately less restrictive than the TPS2121 upstream limit.
  • Schematic symbols are organized by Functional Group and named nets. The current editor's automatic visual placement leaves some support passives separated from their parent ICs; connectivity and grouping are complete, but a later visual-only schematic arrangement pass would improve presentation without changing the circuit.

  • Completion status

  • Primary selected parts

  • Implemented behavior

  • Verification and remaining limitations