Project Start Assistance

can you remove them and fix it?

Thought for 10 sec

Yes—I’ll remove the visible airwires by completing their copper connections, then re-run DRC. I’ll also attempt to repair the three USB copper overlaps; if the protected stale breakout still blocks deletion, I’ll preserve the board and report the exact platform-level blocker rather than hiding it.

Thought for 19 mins 43 sec

Thought for 9 sec

1/3 Repair the protected USB copper overlaps and stale breakout geometry

Repair the protected USB copper overlaps and stale breakout geometry

Route all remaining airwires, including ground and VBUS paths

Re-run DRC and verify zero airwires and shorts

Thought for 12 sec

Thought for 5 sec

Awaiting 1 task

"USB-C PCB Fabrication Fix" completed.

Thought for 4 sec

flux

I couldn’t retrieve and reconcile the completed repair report before the session ended, so I can’t safely claim that its changes removed the 28 airwires or three USB copper overlaps. No additional result has been verified in this turn; the last confirmed board state remains not fabrication-ready.

Remaining work:

Retrieve the completed repair report.
Re-run live DRC to verify airwire and overlap counts.
Confirm USB breakout recovery, VBUS width, ground-plane continuity, and copper repour.
Continue repairs if any violations remain.

Execution stopped because your ACUs ran out.

Files

Schematic

Layout

3D View

Project Specification

Project Overview

Status: Approved for schematic implementation
Production-intent USB-C device sequencer for Raspberry Pi retail audio systems.
Independently connects/disconnects USB 2.0 data and downstream 5 V VBUS under CH340C modem-control outputs.

Intended Use

Unattended retail audio installations.
Upstream Raspberry Pi/SoundWedge host, downstream USB headphones, DACs, or powered speakers.
Supports controlled startup, charging-only operation, test mode, and software-driven recovery from failed enumeration.

What the Device Should Do

Default safely to downstream data disconnected and downstream power off.
DTR controls downstream VBUS; RTS controls the USB 2.0 data switch.
Recommended startup: enable data, wait 100 ms, enable VBUS, then wait for enumeration.
Prefer external 5 V power over host VBUS without backfeeding either source.

Main Features

Four USB-C receptacles: control, host data input, external 5 V power, downstream device output.
480 Mbit/s-capable USB 2.0 high-speed data switch.
3 A-class downstream power path with current limiting and active discharge.
ESD protection on exposed USB data/CC/VBUS interfaces.
Resettable input protection and reverse-current blocking.

System Architecture

Diagram

Hardware Subsystems

Control: CH340C powered from the control port; deterministic pull states enforce OFF/OFF during startup or cable absence.
Data: Bidirectional USB 2.0 high-speed analog switch between J2 and J4, enabled by RTS.
Power: Source selection/isolation followed by a protected, current-limited output switch with quick discharge.
Protection: Low-capacitance USB ESD arrays, VBUS surge protection, resettable input protection, and reverse-current blocking.

Interfaces and Connections

Table

Port	Type-C role	Function
J1 Control	UFP/sink, Rd on CC1/CC2	CH340C control communications and local control power
J2 Host Input	UFP/sink, Rd on CC1/CC2	Upstream USB 2.0 data from Raspberry Pi; optional fallback VBUS
J3 External Power	Sink, Rd on CC1/CC2	Fixed regulated 5 V input; no USB-PD negotiation
J4 Device Output	DFP/source, Rp on CC1/CC2	Downstream USB 2.0 data and switched 5 V power

Power and Runtime Expectations

J3 uses a regulated 5 V USB-C source; no USB Power Delivery controller.
Power-path components and copper shall be rated for at least 3 A continuous downstream capability.
Actual available output current cannot exceed the connected source advertisement/rating and voltage-drop limits.

Power Tree and Power Budget

Table

Path / load	Typical	Design peak
Downstream device on J4	Application dependent	3.0 A
CH340C and control support	=3.0 A continuous

The control electronics should preferentially use J1/J2 power so the full external-power budget remains available to J4.
To guarantee 3.0 A at the load after cable, fuse, mux, and switch losses, the external adapter should have current and voltage margin beyond its nominal 5 V/3 A label.

Manufacturing and Assembly Expectations

JLCPCB-compatible SMD assembly and KiCad export.
Common, active-lifecycle parts with verified footprints and datasheets.
Requested outline target: under 60 mm x 35 mm.
Requested two-layer construction is retained as a cost target, but USB 2.0 HS production robustness requires controlled 90 ohm differential impedance and an uninterrupted reference plane. A four-layer stackup is the engineering default for layout unless the user explicitly accepts the signal-integrity risk of two layers.

Firmware-Relevant Hardware Requirements

DTR = downstream VBUS enable.
RTS = USB data enable.
Hardware pull states must make both functions OFF until software asserts them.
Host software must tolerate active-low modem-signal conventions if imposed by the CH340C driver and invert in hardware or software as required.

Physical Design Expectations

Rectangular PCB, target <=60 mm x 35 mm.
USB-C connectors accessible at board edges; exact edge assignment is deferred to the PCB placement checkpoint.
Keep the high-speed path short, symmetric, and free from plane splits.

Important Design Decisions

Fixed 5 V external input, no USB-PD negotiation.
The board acts as a controlled USB 2.0 interposer: J2 is the upstream-facing Type-C sink role and J4 is the downstream-facing source role.
External power takes priority; host power remains isolated against reverse current.
Data and VBUS controls are independent.

Assumptions

The downstream device supports USB 2.0 audio/data while receiving standard 5 V VBUS.
No USB 3.x SuperSpeed lanes are required.
No BC1.2, proprietary fast-charge, or USB-PD charging modes are required in this revision.
The Raspberry Pi provides ordinary USB host data on J2.

Change Notes

Initial specification derived from the supplied requirements.
Confirmed simplest external-power option: fixed regulated 5 V input, no PD.
Flagged the two-layer versus USB 2.0 HS production-reliability conflict for the layout checkpoint.

Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes