PCB Design Discussion
Scrap the carrier board. Design a standalone PCB from scratch with the ESP32-S3-WROOM-1U module directly on the board. Use all available GPIOs directly — no I2C expanders needed. This gives us full control over pin assignments and avoids the T-Embed's pin limitations.
Use the pin mappings from the HIZMOS project which already proved this works:
- Full SPI bus for CC1101 + nRF24s
- Direct I2C for display + PN532
- Direct GPIOs for buttons, IR, SD card
I accept the extra design effort. Proceed with standalone design.
Thought for 9 sec
I’ll replace the carrier architecture completely with a standalone ESP32‑S3‑WROOM‑1U board, reusing the specified direct GPIO mapping while rebuilding power, charging, display, NFC, storage, dual Sub‑GHz, dual nRF24, IR, controls, and RF layout from first principles.
Worked for 1 min 16 sec
The standalone redesign was planned, but no project mutations were completed because the account ran out of available ACUs. The existing 41-component carrier design remains unchanged.
Remaining work:
- Remove the carrier/bridge architecture.
- Verify ESP32-S3-WROOM-1U-N16R8 GPIO conflicts—especially GPIO35–42 used by octal memory—and finalize a direct-pin remap.
- Rebuild the schematic, power/charging system, radios, display, NFC, SD, controls, and IR.
- Create and route the four-layer 100 × 45 mm PCB.
- Run ERC/DRC and update BOM, firmware, bring-up, and regulatory files.
Document architecture requirements
Identify carrier components
Validate GPIO pin map
Firmware Interface Pin Map
Physical Host Connection
Table
| Host exposed signal | GPIO | Carrier net |
|---|---|---|
| Qwiic SDA | GPIO8 | HOST_I2C_SDA_GPIO8 |
| Qwiic SCL | GPIO18 | HOST_I2C_SCL_GPIO18 |
| Qwiic 3V3 | — | HOST_3V3_SENSE only |
| Qwiic GND | — | GND |
Carrier Internal Mapping
Table
| Function | Device pin/net |
|---|---|
| Shared radio SCK/MOSI/MISO | SC18IS606 SPICLK/MOSI/MISO |
| nRF #1 CSN / #2 CSN / CC2 CS | SC18IS606 CS0 / CS1 / CS2 |
| nRF #1 CE / #2 CE | PCA9555 IO0_0 / IO0_1 |
| CC2 GDO0 / GDO2 | PCA9555 IO0_2 / IO0_3 |
| IR RX / TX | PCA9555 IO0_4 / IO0_5 |
| Expansion GPIO0..2 | PCA9555 IO1_0..IO1_2 |
Incompatible Requested Assignments
GPIO10/11/12/13/16/17/35/36/40/41/42 are not documented on the exposed host connectors. GPIO18 is exposed but is host I2C SCL, not a dedicated SPI clock. Therefore all requested direct GPIO assignments are rejected in this no-host-modification carrier.
Startup
- Initialize host I2C on GPIO8/18.
- Configure PCA9555: CE1=0, CE2=0, IR_TX=0; inputs for GDO/IR_RX.
- Initialize SC18IS606; set CS outputs inactive high and conservative SPI clock.
- Probe one radio at a time.
- Enforce IR duty/current interlock and avoid simultaneous maximum radio PA + IR bursts.
Physical Host Connection
Carrier Internal Mapping
Incompatible Requested Assignments
Startup