# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** interlock - **Created:** 3/6/2024 - **Last Updated:** 3/6/2024 - **Visibility:** Public ## Key Components ### — [STEF512PUR](https://www.flux.ai/interlock/stef512pur~sl.md) **Pins:** - EN - GND - IMON_12 - IMON_5 - SS12 - SS5 - VIN_5 - VOUT_12 - VOUT_12 - VOUT_5 *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/interlock/2-layer-jlcpcb-constraints~70](https://www.flux.ai/interlock/2-layer-jlcpcb-constraints~70).* --- *Generated from [https://www.flux.ai/interlock/2-layer-jlcpcb-constraints~70](https://www.flux.ai/interlock/2-layer-jlcpcb-constraints~70)*