Raspberry Pi HAT Design
Thought
flux
Work completed
- Removed Waveshare connector and associated nets
- Added raw 2.9" e-paper FPC connector placeholder (J2) with pins Gx, Sx, VCOM, VGL, VGH, VDD, RES, CLK, DIN, CS, AUX
- Placed TI TPS65185RSLR as the e-paper driver/PMIC (U6)
- Added supporting passive components:
- Capacitors C17, C18, C19, C20, C21
- Series damping resistor R9 on SCLK
- Pull-ups R10 on BUSY and R11 on RST
- Wired PMIC power rails:
- U6:VGH to FPC VGH
- U6:VGL to FPC VGL
- U6:VCOM to FPC VCOM
- U6:VIN to boost converter 5 V net
- U6:VIN3P3 to Pi 3.3 V net
- Rewired Pi SPI and control lines through driver and FPC connector:
- MOSI, MISO, SCLK (via R9), CS, DC, RST, BUSY remapped to J2 pins
- Added test points for MOSI, MISO, SCK, CS, DC, RST, BUSY
- Renamed nets to PANEL_MOSI, PANEL_MISO, PANEL_SCLK, PANEL_CS, PANEL_DC, PANEL_BUSY
- Documented FPC connector orientation and added layout keepout note: "Maintain 5 mm clearance for high-voltage nets (VGH, VGL, VCOM)"
Success criteria
✅ Waveshare connector replaced with raw FPC connector
✅ High-voltage rails (VGH, VGL, VCOM) implemented via PMIC
✅ SPI (with series damping) and control signals correctly rewired
✅ ERC validation and BOM placeholders integrated
✅ High-voltage rails (VGH, VGL, VCOM) implemented via PMIC
✅ SPI (with series damping) and control signals correctly rewired
✅ ERC validation and BOM placeholders integrated
Next step
Proceed to PCB layout: review footprints, configure stackup, place components, and set up Auto-Layout for routing.
Proceed to PCB layout: review footprints, configure stackup, place components, and set up Auto-Layout for routing.
Thought
Thought
flux
Work completed
- Removed Waveshare connector and associated nets
- Added raw 2.9" e-paper FPC connector placeholder (J2) with pins Gx, Sx, VCOM, VGL, VGH, VDD, RES, CLK, DIN, CS, AUX
- Placed TI TPS65185RSLR as the e-paper driver (U6)
- Added supporting passive components:
- Capacitors C17, C18, C19, C20, C21
- Series damping resistor R9 on SCLK
- Pull-ups R10 on BUSY and R11 on RST
- Wired PMIC power rails:
- U6:VGH to FPC VGH
- U6:VGL to FPC VGL
- U6:VCOM to FPC VCOM
- U6:VIN to boost converter 5 V net
- U6:VIN3P3 to Pi 3.3 V net
- Rewired Pi SPI and control lines:
- MOSI, MISO, SCLK (via R9), CS, DC, RST, BUSY remapped to J2 pins
- Added test points for MOSI, MISO, SCK, CS, DC, RST, BUSY
- Renamed nets to PANEL_MOSI, PANEL_MISO, PANEL_SCLK, PANEL_CS, PANEL_DC, PANEL_BUSY
- Documented FPC connector orientation and added layout keepout note: "Maintain 5 mm clearance for high-voltage nets (VGH, VGL, VCOM)"
Success criteria
✅ Waveshare connector replaced with raw FPC connector
✅ High-voltage rails implemented via PMIC
✅ SPI (with series damping) and control signals correctly rewired
✅ ERC passes and BOM placeholders integrated
✅ High-voltage rails implemented via PMIC
✅ SPI (with series damping) and control signals correctly rewired
✅ ERC passes and BOM placeholders integrated
Next step
Prepare PCB layout: review footprints, set up stackup, place components, and run Auto-Layout for routing.
Prepare PCB layout: review footprints, set up stackup, place components, and run Auto-Layout for routing.
