Tuya RS485 Sensor PCB

flux

I can build this as a separate proof-of-concept project: 12 VAC input, protected rectifier/power supply, Tuya Wi‑Fi module, isolated/protected RS‑485 interface, one power LED, and one pairing/reset button on a simple long narrow PCB.
The PDFs could not be text-extracted in Chat mode, so I need Agent mode to inspect the protocol/registers, create the new project, select parts, build and verify the schematic, then make the basic PCB. Click Continue in Agent Mode and I’ll proceed; I’ll only stop for clarification if the sensor’s wire pinout or required measurement variant cannot be established from the attachments.
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flux

I’ll extract the sensor wiring/protocol, create a separate proof-of-concept project, build and verify the schematic, then make a simple long narrow PCB layout.
Created a thread, a project
Tuya Inline Chemical Sensor POC

Tuya Inline Chemical Sensor POC

Proof-of-concept long narrow Tuya Wi-Fi interface board for a 4-wire chemical sensor using MODBUS-RTU over RS-485. Powered from external Class 2 12 VAC, with...
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illuminex2026

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Build chemical sensor POC schematic
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flux

The sensor interface is confirmed: 9–24 VDC probe power, yellow/green RS‑485, and MODBUS‑RTU at 9600‑8‑N‑1. The new project is created, and I’m finishing the power and communications schematic verification now.

flux

The verified 39-component schematic is complete in Tuya Inline Chemical Sensor POC. It uses 12 VAC input, rectified probe power, a 3.3 V buck, Tuya CBU, protected RS‑485, one power LED, and one pairing/reset button.
For the first PCB, I propose a simple 2-layer rectangular board around 100 × 25 mm, components on both sides, cable connections at opposite ends, and the CBU antenna at the outer edge. I’ll also correct the CBU footprint’s undocumented center pad before placement—confirm this layout plan and I’ll proceed.
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KiCad Schematic Review
Scope
Review of the uploaded test1.kicad_sch only. No PCB file, ERC report, BOM, or datasheets were included, so PCB geometry, actual land patterns, routing, antenna clearance, and full electrical-limit verification remain outside this review.
Overall assessment
The design is logically divided into power, pH/ORP buffers, ADC, flow input, temperature input, Tuya CBU, and display sections. The architecture is understandable, but the file is not ready for PCB fabrication. The largest immediate problem is footprint/library integrity: many symbols have footprints belonging to completely unrelated components.
Critical findings
1. Numerous footprint assignments are invalid
These errors can produce an unusable PCB even if the schematic connectivity is correct.
  • U1 and U2 (LMP7721): custom symbols expose eight pins, but both use a SOT-23-6 footprint. An eight-pin device cannot map correctly onto six pads.
  • Tuya CBU module: assigned PLCC-84_29.3x29.3mm_P1.27mm, which is unrelated to the CBU module land pattern.
  • R1, R2, R4 and R5: assigned a DIP-8 footprint rather than individual resistor footprints.
  • C2, C3, C4, C6, C9, C10, C11 and C12: several are assigned SOT-223 regulator footprints.
  • C1 (1000 uF): assigned an LFCSP-16 IC footprint. This is physically and electrically invalid.
  • J2 and J3 coaxial probe connectors: assigned a Tag-Connect programming footprint rather than the intended BNC/coax connector.
  • J4, J5, J6 and J7: several generic connectors use the same three-contact XLR footprint despite having three, four, or eight schematic pins.
  • D1, F1, L1, R3, R6, R7 and R8: have no usable footprint assigned.
  • Some power-symbol objects also contain footprint metadata. Power symbols should not create physical PCB parts.
Required action: audit every BOM component using KiCad’s symbol-fields table, select the exact manufacturer part, and assign a verified footprint with matching pad count and pin numbering.
2. The custom LMP7721 symbol requires verification
The custom symbol has unusual pin electrical types and geometry. Pins labelled NC and guard-related pins are represented as power/passive pins, and the output/guard geometry appears ambiguous. Incorrect custom-symbol pin numbers are especially dangerous because the pH/ORP channels depend on femtoamp-class input behavior.
Verify the symbol pin numbers, package variant, guard pins, exposed/NC pins, supply pins, and output against the exact LMP7721 ordering code. Do not proceed using the current SOT-23-6 assignment.
3. pH/ORP inputs need contamination and protection planning
Using an LMP7721-class amplifier is directionally appropriate for very-high-impedance probes, but normal PCB practices are insufficient.
  • Provide a driven guard around the sensitive input node where supported by the verified device configuration.
  • Keep solder mask openings, flux residue, moisture paths, connector contamination, and conformal-coating leakage in mind.
  • Avoid placing ordinary clamp diodes directly on the electrode input unless their leakage is proven acceptable.
  • Add a documented input-protection strategy for ESD and accidental connection without compromising input bias current.
  • Keep switching-regulator, Wi-Fi, display, and digital-return currents far from the electrode input region.
For a wet/outdoor product, moisture leakage can dominate the intended signal unless the analog region is carefully guarded, cleaned, coated, and mechanically isolated.
4. Power-input protection is incomplete or unspecified
The input shows a fuse, bridge rectifier, bulk capacitor, AP63205 5 V buck, and AMS1117 3.3 V regulator. That is a reasonable block-level sequence, but the actual protective parts and ratings are not defined.
  • F1 is only named Fuse; its current, voltage, interrupt rating, hold/trip behavior, and footprint are missing.
  • D1 has no selected bridge-rectifier part or footprint.
  • There is no clearly identified surge/TVS component at the external power input in this file.
  • Confirm the worst-case rectified DC voltage from the maximum 12 VAC transformer output at light load, including mains tolerance and transformer regulation.
  • Confirm C1 voltage rating and ripple-current rating. 1000uF 25V may have limited margin depending on the real transformer’s no-load output and surge environment.
  • Verify AP63205 input voltage, inductor saturation current, capacitor voltage/bias derating, bootstrap capacitor connection, and recommended layout directly against the datasheet.
Use a UL Listed Class 2 external 12 VAC transformer so the PCB remains SELV/Class 2, but still design the input for outdoor wiring transients.
5. AMS1117 is a weak choice for the 3.3 V Wi-Fi rail
The AMS1117 can work from 5 V, but it dissipates (5 V - 3.3 V) × current. Wi-Fi modules have burst current, making thermal performance and transient droop important. It is also relatively inefficient and may require specific output-capacitor characteristics depending on the actual manufacturer.
A modern regulator with verified transient response and enough peak-current margin is preferable. If the AMS1117 remains, calculate worst-case dissipation, copper-area thermal resistance, dropout, capacitor ESR/stability, and CBU peak-current behavior.
6. Tuya CBU symbol and programming connections need verification
The module uses a custom symbol with an unusual reference string and no datasheet metadata. Verify every pin number against the exact CBU/CBU-IPEX variant. Confirm:
  • 3.3 V and all ground pads
  • CEN/reset default state
  • UART programming/test access
  • boot and strapping requirements
  • selected SPI display pins
  • antenna or IPEX keepout and RF ground requirements
  • local bulk plus high-frequency decoupling at the module
The schematic should include an unambiguous programming/test interface and named nets rather than labels such as J7_4, J7_5, and U5_10.
7. ADC implementation needs cleanup and explicit channel naming
The ADS1115 is suitable for low-bandwidth sensing, but the channel usage is difficult to follow from the present wiring.
  • Rename AIN nets by function, such as PH_ADC, ORP_ADC, and any spare/auxiliary channel.
  • Verify that every input remains between GND and VDD under all probe and fault conditions.
  • Confirm whether readings are single-ended around 1.65 V or differential; document the expected voltage range.
  • Add a 100 nF local VDD capacitor directly at U3 and consider local bulk capacitance.
  • Confirm ADDR pin state and expected I2C address.
  • The 4.7 kΩ I2C pull-ups are reasonable as a starting point, but bus capacitance and voltage domains must be checked.
8. Flow and temperature external interfaces lack robust field protection
The connectors expose power, ground, and logic to cables. External cables can inject ESD and surge energy.
  • Add suitable low-capacitance ESD/TVS protection at the connector boundary.
  • Add series resistance and filtering close to the receiving GPIO.
  • Verify whether the flow sensor is open-collector, push-pull, 5 V, or 3.3 V. The shown 10 kΩ pull-up to 3.3 V and 1 kΩ series resistor may be appropriate only for certain sensor types.
  • Verify the temperature-sensor protocol and supply range. If it is a 1-Wire device, document the pull-up and cable-length constraints.
  • Define connector pin numbers and signal names explicitly.
9. Display interface needs a real connector and signal-integrity review
J7 is an eight-pin display connector but currently uses a three-pin XLR footprint. Correct the connector first. Then verify the exact display voltage, backlight current, logic levels, pin order, and whether BACKLIGHT requires a transistor/current-limiting circuit rather than direct GPIO drive.
10. Schematic-library hygiene and readability
The schematic includes generic labels (J7_3, J7_4, U5_9, U5_10) and custom parts without values, datasheets, or descriptions. This makes review, firmware, manufacturing, and service harder.
  • Use normal references such as U6 for the Tuya module.
  • Give every physical component a value/MPN, verified footprint, datasheet, tolerance, voltage/current rating, and package.
  • Remove footprints accidentally stored on power symbols.
  • Use net names based on function rather than component-pin coordinates.
  • Run annotation, ERC, footprint-assignment checks, and pin-count comparison after cleanup.
Positive aspects
  • Clear functional grouping makes the intended system understandable.
  • Full-wave rectification allows a non-polarized 12 VAC input.
  • Buck conversion before the 3.3 V stage is more efficient than regulating directly from rectified AC.
  • ADS1115 provides adequate resolution and programmable gain for slow electrochemical measurements.
  • Separate pH and ORP buffer channels are conceptually appropriate.
  • Basic pull-ups and local filtering are present in several interfaces.
  1. Fix every symbol, reference, pinout, and footprint mismatch.
  2. Verify the LMP7721 and Tuya CBU custom symbols against authoritative datasheets.
  3. Recalculate and finalize the complete power path and input protection.
  4. Finalize pH/ORP guarding, leakage control, and probe protection.
  5. Define the exact flow, temperature, display, and programming connectors.
  6. Add cable-interface ESD/transient protection.
  7. Run KiCad ERC and resolve all errors rather than suppressing them.
  8. Review the PCB placement/routing separately, with special attention to the Wi-Fi antenna, buck-converter hot loop, and high-impedance analog area.
Verdict
The architecture is a useful early prototype concept, but the project should not be fabricated in its current form. The footprint mismatches alone guarantee major assembly problems, and the custom high-impedance analog and wireless-module symbols need authoritative pinout verification before layout.

  • Scope

  • Overall assessment

  • Critical findings

  • 1. Numerous footprint assignments are invalid

  • 2. The custom LMP7721 symbol requires verification

  • 3. pH/ORP inputs need contamination and protection planning

  • 4. Power-input protection is incomplete or unspecified

  • 5. AMS1117 is a weak choice for the 3.3 V Wi-Fi rail

  • 6. Tuya CBU symbol and programming connections need verification

  • 7. ADC implementation needs cleanup and explicit channel naming

  • 8. Flow and temperature external interfaces lack robust field protection

  • 9. Display interface needs a real connector and signal-integrity review

  • 10. Schematic-library hygiene and readability

  • Positive aspects

  • Recommended correction order

  • Verdict