NAVC Escape Root Cause and Minimum Move Plan
Why the local rip-up still failed
The failure is not caused by a NAVC1 footprint keepout. Inspection found no project-local keepout or protected-area rule targeting NAVC1 or SWD2, and preflight reported no ROUTING_PIN_INSIDE_KEEPOUT, ROUTING_UNROUTABLE_PIN, or boundary anomaly.
The dominant rule/geometric constraints are:
-
Effective copper clearance is 0.5 mm, not the visible 3.8 mil universal rule.
- The project rule
Auto-Layout: Universal Keepout requests 3.8 mil (~0.097 mm), minimum 3.5 mil.
- However, system defaults impose
minKeepOut: net(0.5mm) on traces, pads and vias.
- Therefore the router must maintain approximately 0.5 mm net-to-net clearance around every existing pad, via and trace. This dominates the 0.15 mm trace width and explains why narrowing the target trace did not create a path.
-
Via geometry is large relative to the escape pitch.
- Through-vias are 0.6 mm pads with 0.3 mm drills.
- With the 0.5 mm minimum clearance, each via consumes an effective obstacle diameter of roughly 1.6 mm between unrelated nets.
- Hundreds of duplicate-via preflight warnings confirm the imported autoroute has excessive/duplicated via positions. The router deduplicates them internally, but their persisted copper topology still makes the NAVC region highly fragmented.
-
The local rip-up removed target-net copper, not the unrelated copper walls.
- Removing 180 nodes from SWDIO, NRST, BAR reset and I2C1 SCL reduced the pathfinder obstacle count only from ~6,290 to ~6,115.
SWCLK, SWDIO, and NRST still had no continuous 0.5 mm-clearance corridor because unrelated +3V3/GND/USB/GPIO traces and vias remained around NAVC1.
-
The NAVC1-to-SWD2 corridor is physically pinched by fixed parts.
- NAVC1 center:
(-4.4, -12.5) mm
- SWD2 current center:
(-27.1, -25.1) mm
- Fixed corridor boundaries:
I2C3_NAVC1 at (-16.1, -25.5), GPS_NAVC1 at (-5.2, -25.0), and crystal network C52/C53 around (-12, -21.5) / (-8.95, -20.9).
- The remaining adjustable choke point is the bottom-side passive row around C46/C47 and the SWD2 approach angle.
Smallest specific placement plan
Apply in this order and validate after each step.
1. SWD2: complete the full 2 mm upward displacement
Current: (-27.1, -25.1) mm
Proposed: (-27.1, -23.6) mm, same rotation.
This is an additional 1.5 mm upward move, giving a total 2.0 mm shift from its original y=-25.6. The prior 0.5 mm move was too small to change the approach topology. At y=-23.6, the SWD2 pads align above the I2C3_NAVC1/GPS_NAVC1 connector line and provide a more direct west-to-east corridor for SWCLK, SWDIO and NRST.
2. C46: move 1.5 mm north simultaneously with the full SWD2 move
Current: (-8.95, -16.03) mm
Proposed: (-8.95, -14.53) mm, same rotation.
C46 alone did not solve routing, but paired with the full SWD2 move it opens the southwest NAVC1 fan-out lane while leaving fixed crystal components C52/C53 untouched.
3. R37: move west and slightly north, not west-only
Current: (8.0, -6.5) mm
Proposed: (5.0, -5.0) mm, same rotation.
The earlier (5.0, -6.5) trial made BAR reset geometrically routable, proving the westward shift is useful, but the pad landed on existing USB/I2C copper. Adding a 1.5 mm north component avoids the specific copper band that caused the overlap while keeping R37 closer to NAVC1:PB0.
Optional fourth move for nearby NAVC1 signals
Only if GPIO/LED/I2C pins still cannot escape after moves 1–3:
- Move
C47 1.5 mm east, from (-5.0, -16.03) to (-3.5, -16.03) mm, same rotation.
This creates a second vertical breakout gap below NAVC1 without moving NAVC1, GPS_NAVC1, I2C3_NAVC1, C52, C53, or any crystal component.
Rule conclusion
- No footprint keepout is blocking NAVC1.
- The main rule blocker is the inherited 0.5 mm minimum copper clearance, combined with 0.6 mm through-vias and dense unrelated copper.
- A rule-only solution would require a scoped clearance reduction for NAVC debug nets and their local vias; trace width alone cannot overcome the 0.5 mm minimum.
- If manufacturing rules permit, a scoped 0.15–0.20 mm clearance override around the three debug nets would likely reduce the required placement movement. Without changing clearance, the combined SWD2 + C46 moves above are the smallest credible placement solution.