Airwire Fix

tankdestroyer99999999

tankdestroyer99999999

Fix all the overlpas flaoting coppers and airwires

flux

I’ll resolve the fixed-geometry overlaps and floating copper first, then clean stale traces, route the remaining connections, and finish with a full ERC/DRC verification.

flux

Copper geometry is clean. Routing preflight found 293 duplicate-via records from the imported layout; I’m removing those duplicates before routing so the router does not build on corrupted transitions.

flux

Overlap and copper cleanup completed:
  • Overlapping copper: 0
  • Floating copper: 0
  • Dangling traces: 0
  • Airwires: 54
Routing is blocked by 293 duplicate-via records in the imported layout. The preflight exposes their coordinates but not enough UID/net data to safely remove only the duplicates, so I did not risk deleting valid vias. A dedicated duplicate-via cleanup capability or manual editor cleanup is required before safely routing the 54 airwires.
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Schematic

Layout

Preview

Final PCB Engineering Review
Verified state
Review timestamp: 2026-07-28 06:14 UTC.
  • Copper overlaps: 0
  • Floating copper: 0
  • Dangling traces: 0
  • Airwires / DRC errors: 51
  • ERC errors: 10
  • Manufacturing readiness: Not ready — unrouted electrical connections remain.
Airwire analysis by physical region
1. NAVC MCU and LED/GPIO support bank
This is the largest pad-to-pad cluster. It includes BOOT0, GPIO A/B/C/D/E/F/H, LED A/B/C/D, LED cathode-to-resistor links, HSE_OUT, INT_GYR, I2C3 SCL/SDA, UART1/UART3, SAFEBOOT and related support connections around NAVC1, R26/R30–R36/R40–R47, LED9–LED12, U5/U10/U12 and I2C3_NAVC1.
Root cause: dense existing copper and limited escape corridors around NAVC1 and the separated bottom-side resistor bank. The deterministic local router previously reported thousands of obstacles for this region. Moving the bank made one route possible but produced stale-copper violations, so that placement pass was reverted and the stale bank copper was removed.
Classification:
  • B — Requires local rerouting: short LED/resistor links and nearby bank links after deliberate local copper clearance.
  • C — Blocked by placement congestion: long NAVC1-to-bank and NAVC1-to-peripheral links where fixed existing routes occupy the escape channels.
  • D — Manual engineering judgement: crystal HSE_OUT and routes that may require selecting/removing specific nearby working segments to preserve clock-loop quality.
2. FCC MCU / peripheral and PWM cluster
Includes I2C2/FCC links, PWM7 data to U2, UART5/header-related fragments, and several airwires whose endpoint is an existing trace island rather than a directly addressable pad.
Root cause: the remaining connectivity is split between already-routed copper islands. The surgical router accepts pad-to-pad endpoints only, so trace-to-trace and trace-to-via airwires cannot be directly completed without identifying and rerouting the parent net segment.
Classification:
  • B — Requires local rerouting: pad-to-pad FCC/peripheral links once their exact endpoint pair is exposed.
  • D — Manual engineering judgement: trace-island endpoints, because the blocking/parent route must be selected before copper is deleted.
3. Power and ground islands
Several remaining airwires are on +3V3/GND and terminate at trace or via endpoints.
Root cause: previous imported/reconstructed copper forms multiple disconnected islands. The three genuinely floating islands were deleted, but net-assigned disconnected islands remain and are correctly reported as airwires.
Classification:
  • B — Requires local rerouting: short pad-to-island power stitches where the intended branch is clear.
  • D — Manual engineering judgement: selecting which existing power island should be the trunk, to avoid creating poor return paths or redundant loops.
4. Crystal / clock region
HSE_IN/HSE_OUT related airwires remain around the MCU/crystal networks.
Root cause: sensitive short-loop routing is constrained by existing copper and separated support parts.
Classification: D — Manual engineering judgement. These should be manually routed with short, direct geometry and minimal vias rather than forced around unrelated obstacles.
Automatically routable versus blocked
Automatically routable now
No remaining connection can be safely declared automatically routable without a fresh route attempt and post-route overlap check. The prior successful LED9 route depended on a placement change that was reverted.
Requires local rerouting
  • LED9–LED12 series-resistor nets and LED control nets.
  • NAVC GPIO/boot/I2C/UART links with pad-to-pad DRC endpoints.
  • FCC/PWM pad-to-pad links.
Blocked or requires manual routing
  • Airwires whose DRC endpoint is a trace/via UID rather than a component pad.
  • Power/GND island stitching.
  • Crystal routes.
  • Long NAVC routes through the existing dense copper field.
Intentional airwires
None have been confirmed intentional.
ERC review
  1. U10:VIO_SEL, net: none — power input pin is unconnected. Likely not intentional unless the MAX-M10S variant explicitly permits the pin to float. Recommended: verify datasheet strap requirement and connect to the specified rail/strap.
  2. REG1:VDD, net Net-(C4-Pad1) — power input net has no recognized source. Likely a power-source declaration issue or missing connection. Verify regulator datasheet and input rail topology.
  3. REG1:PVDD, net Net-(C3-Pad1) — power input net has no recognized source. Likely a power-source declaration issue or missing connection. Verify intended VIN connection.
  4. U5:VDD, net UART3_FCC1 1 - UART4_FCC1 1 — VDD is on a suspiciously named mixed net. Likely not intentional and may indicate an import/net reconstruction error. Requires schematic correction after design-owner review.
  5. U11:VCC, net Net-(C67-Pad2) — no recognized source. Likely not intentional; verify USB-derived VCC rail and connect/declare its source.
  6. U12:VCC, net Net-(C69-Pad2) — no recognized source. Likely not intentional; verify USB-derived VCC rail and connect/declare its source.
  7. C57:P2, net Net-(C57-Pad2) — single-pin net. Likely an orphan from a missing/imported component terminal.
  8. NAVC1:PA6, net INT_MAG_NAVC — single-pin interrupt net. Likely an orphan from the absent/mis-imported magnetometer U8.
  9. C59:P1, net Net-(C59-Pad1) — single-pin net. Likely an orphan from a missing/imported component terminal.
  10. C57:P1, net Net-(C57-Pad1) — single-pin net. Likely an orphan from a missing/imported component terminal.
No ERC was automatically changed because the architecture and schematic are frozen and none of these corrections is electrically unambiguous without the original design intent/datasheet mapping.
Manufacturing verification
The board currently has no copper shorts, floating copper, or dangling traces, but 51 unrouted connections are a hard manufacturing release blocker. Gerber generation may be mechanically possible, but the board would not be electrically complete.
Perform manual interactive routing in region order: (1) LED/resistor bank, (2) NAVC GPIO/UART/I2C, (3) FCC/PWM trace-island reconnection, (4) power/GND island stitching, and (5) crystal routes last with strict loop control. After each region, run overlapping-copper and airwire DRC before proceeding.

  • Verified state

  • Airwire analysis by physical region

  • 1. NAVC MCU and LED/GPIO support bank

  • 2. FCC MCU / peripheral and PWM cluster

  • 3. Power and ground islands

  • 4. Crystal / clock region

  • Automatically routable versus blocked

  • Automatically routable now

  • Requires local rerouting

  • Blocked or requires manual routing

  • Intentional airwires

  • ERC review

  • Manufacturing verification

  • Recommended next action