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Smart Chair Hardware Design Discussion

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Creating the hardware design document.

Ergonix Smart Chair V1 — Hardware Design Description

Overview

Product: Ergonix Smart Chair V1 – smart seat module for occupancy, posture, and pressure distribution.
Board: 2-layer target, 80 mm × 60 mm, USB‑C powered (5 V only), 3.3 V logic.
Architecture: ESP32‑C3 module + I2C IMU + 4× FSR analog inputs + USB‑C power and ESD + JST‑PH harness connectors + LEDs, reset, and programming pads.
Project stage: Pre‑prototype to Pilot (50–100 units); sourcing through LCSC for JLCPCB assembly.

MVP functions

Occupancy detection: FSR-based presence and basic thresholding.
Sitting duration tracking: Periodic BLE updates to the app.
Basic pressure mapping: 4 zones (front-left, front-right, back-left, back-right).
Posture/tilt detection: IMU tilt channels (pitch/roll/yaw as needed).
BLE connectivity: BLE link to the mobile app at 1 Hz for sensor data.

Major hardware blocks

MCU module: U1 ESP32‑C3‑WROOM‑02‑N4 (primary), fallback U2 ESP32‑C3‑WROOM‑02U‑N4 for external antenna option.
IMU: U3 MPU‑6050 over I2C.
Power input and protection:
- USB‑C receptacle: J1.
- Data‑line ESD: D1 (protects D+/D− at the connector; data not used in V1).
- VBUS TVS: D4 clamps input surges.
- CC sink resistors: R19 (CC1→GND), R20 (CC2→GND).
- 3.3 V LDO: U4 NCP176BMX330TCG with local decoupling C1–C4.
Sensor interfaces:
- FSR harness: J2 JST‑PH 6‑pin (4× FSR + VCC + GND).
- I2C/power harness: J3 JST‑PH 4‑pin (SDA, SCL, VCC, GND).
User interface and debug:
- LEDs: D2, D3 with series resistors R17, R18.
- Reset: SW1 to U1:EN.
- Programming test pads: TP_PROG_TX, TP_PROG_RX, TP_BOOT, TP_EN.
Grounds and return: GND single reference plane with short ESD return paths near the USB‑C connector.

Power and USB‑C (power‑only)

USB‑C sink behavior: Separate CC lines with Rd resistors:
- R19 ties CC1→GND
- R20 ties CC2→GND
ESD/Surge: D1 on D+/D−; D4 on VBUS.
Regulation: U4 generates 3.3 V; decouple with C1–C4 close to IN/OUT and add local 100 nF near U1 and U3.
Native USB note: For V1, USB data is not connected to ESP32‑C3; programming uses UART test pads.

I2C bus and peripherals

Signals:
- SCL: U1 IO4 on net “SCL”; pulled up via R22 to 3V3; available on J3 pin 1; to U3:SCL.
- SDA: U1 IO5 on net “SDA”; pulled up via R23 to 3V3; available on J3 pin 2; to U3:SDA.
Pull‑ups: 4.7 kΩ typical, placed near U1. Keep total bus capacitance within spec; the 30–50 cm harness is accounted for.

FSR analog front‑end (4 channels)

Harness: J2 carries 4 FSR sense lines plus power and ground.
Per‑channel network (example, same pattern for all four):
- Divider and sense/filter:
  - Channel 1 (FSR1): R13, R7, C6
  - Channel 2 (FSR2): R14, R6, C7
  - Channel 3 (FSR3): R15, R5, C8
  - Channel 4 (FSR4): R16, R9, C5
Notes:
- Series/input protection and RC filtering mitigate noise from long harness runs.
- ADC sampling at 1 Hz target; firmware to average a few samples for noise reduction.
- Calibration: per‑user software calibration; optional BOM‑tunable resistor footprints for range adjustments.

User interface, reset, and programming

LEDs:
- Power/heartbeat: D2 via R17.
- Status/BLE: D3 via R18.
Reset:
- SW1 to U1:EN with proper pull‑up.
Programming/test:
- UART: TP_PROG_TX (TXD), TP_PROG_RX (RXD).
- Boot mode: TP_BOOT (IO0), TP_EN (EN).

Pin map summary (current)

ESP32‑C3 core pins (project nets):
- I2C: IO4 = SCL, IO5 = SDA.
- Programming: IO21 = PROG_TX (UART0 TX), IO20 = PROG_RX (UART0 RX), IO0 = BOOT, EN = reset.
- LEDs: IO6, IO7 used for indicator control.
- FSR: Four ADC channels wired to nets FSR1–FSR4 via the front‑ends listed above.
Boot/strapping caution: IO0 and EN are strap/reset; avoid heavy loads or fixed external states during reset.

RF and antenna plan

Primary: U1 integrated PCB antenna at a board edge with a datasheet‑compliant keep‑out (no copper/vias/components in front of the antenna).
Metal frame proximity: Validate RSSI/packet loss with the board mounted; if detuning occurs, pivot to U2 (external antenna option) with a remote antenna position away from metal.

Connectors, harnessing, and mechanical

USB‑C: J1 for power‑only.
FSR harness: J2 6‑pin JST‑PH; route entries away from RF edge; add silkscreen pin‑1 marking.
I2C/power harness: J3 4‑pin JST‑PH; exposes SDA/SCL/VCC/GND for IMU or expansion.
Mounting: Place holes to avoid antenna aperture and thick structural members; keep cable egress clear of antenna region.

ESD, protection, and grounding

USB:
- D+/D− protected by D1 at connector side (low‑capacitance ESD).
- VBUS protected by D4; consider inline fuse on VBUS if needed.
CC detection:
- Separate CC1/CC2 via R19, R20 to GND.
Ground strategy:
- Single reference plane; short ESD return to J1; keep analog returns (FSR filters) close to the plane and away from high‑dv/dt paths.

BOM and sourcing snapshot

All mains are LCSC‑backed; designed for JLCPCB assembly at qty‑100. Key line items by designator:
- MCU: U1; fallback U2.
- IMU: U3.
- LDO: U4.
- USB‑C: J1.
- TVS: D4; ESD array D1.
- Harness: J2, J3.
- I2C pull‑ups: R22, R23.
- CC resistors: R19, R20.
- LEDs/resistors: D2, R17; D3, R18.
- FSR front‑end parts: R5, R6, R7, R9, R13, R14, R15, R16, C5, C6, C7, C8.
- Decoupling: C1–C4.
- Reset: SW1.
Availability: Selected parts are common and stocked; alternates can be added if any supply constraints arise at order time.

Firmware data and update cadence

BLE data at 1 Hz: 4 FSR channels + basic IMU tilt; occupancy and duration counters as needed.
Programming path: UART via TP_PROG_TX/TP_PROG_RX with TP_BOOT and TP_EN. Native USB not used in V1.

Test and calibration plan (bring‑up)

Power/USB: Verify no shorts; measure 5 V at J1 and 3.3 V at U4:OUT.
Programming: Confirm boot into UART download with IO0 low at reset; flash a simple LED blink on D2/D3.
I2C/IMU: Scan bus; read WHO_AM_I from U3.
FSRs: Confirm analog ranges with known loads; perform software baseline calibration.
RF soak: 8+ hour BLE link stability in chair frame environment; log RSSI/packet loss.

Layout and DFM notes

Antenna: Keep‑out per module datasheet; place U1 at a board edge with no copper/vias/components in front of the antenna.
Analog vs digital: Keep FSR entries and RC filters away from USB and switching currents; short, direct ground returns to the plane.
ESD: Place D1 and D4 close to J1 with minimal inductance in the return path.

Open items and next steps

Finalize routing and silkscreen keep‑out markings for the antenna aperture.
Confirm I2C and FSR pin assignments at firmware integration time; avoid sharing IO6 between LED and FSR in the next spin if possible.
Export manufacturing package: Gerbers, Pick‑and‑Place, and BOM CSV with LCSC numbers; attach assembly notes for the harness orientation and antenna placement.

Revision control

Current intent: V1 power‑only USB‑C, 4× FSR channels, integrated antenna primary, external antenna fallback via U2. Any changes to pin mapping or parts will be recorded in the project properties and reflected in the BOM.

This description reflects the current design state and is intended for internal alignment, firmware planning, purchasing (LCSC/JLCPCB), and mechanical integration.

shorter executive summary

firmware interface details

manufacturing notes expansion

test procedure checklist

mechanical constraints

59 days

Ready.

TP_PROG_TX

Capacitance

100nF

R10

Resistance

10k Ω

J2 Pin_6 - R9 P1

Capacitance

100nF

J2 Pin_5 - R5 P1

PROG_BOOT

J2 Pin_3 - R7 P1

SW1 2 - GND GND

U4 OUT - U1 3V3

J2 Pin_4 - R6 P1

Resistance

10k ohms

Capacitance

100nF

PROG_BOOT

Resistance

10k Ω

Capacitance

100nF

Capacitance

100nF

Resistance

10k Ω

U1 IO9 - U3 SDA

TP_PROG_RX

U1 EN - SW1 1

Resistance

10k Ω

J1 D2+ - D1 CATHODE_4

SW1 2 - GND GND

R11

Resistance

10k Ω

Resistance

10k Ω

TP_EN

PROG_TX

R12

Resistance

10k Ω

Resistance

10k Ω

TP_PROG_TX

Resistance

4.7k ohms

PROG_BOOT

U1 EN - SW1 1

Resistance

4.7k ohms

PROG_RX

J2 Pin_3 - R7 P1

J2 Pin_6 - R9 P1

SW1 2 - GND GND

U1 EN - SW1 1

Capacitance

100nF

SW1 2 - GND GND

J2 Pin_5 - R5 P1

SW1 2 - GND GND

PROG_RX

Capacitance

100nF

Resistance

10k Ω

J2 Pin_5 - R5 P1

U1 IO8 - U3 SCL

Capacitance

100nF

J2 Pin_4 - R6 P1

J2 Pin_6 - R9 P1

GND

SW1

Reviews

Electrical Rule Checks

Missing Footprints

Reports components that need a footprint but don't have one.

Design Rule Checks

Overlapping Copper • 54

Des	Net	Des	Net
R22:P2	3V3	Trace 8f9b	FSR3
R23:P2	3V3	SW1:2	GND
SW1:1	EN	Trace fc20	FSR1
SW1:1	EN	Via	None
J2:Pin_3	FSR1	Trace e9f5	SCL
R13:P1	FSR1	J2:Pin_6	FSR4
Trace 774f	FSR1	C7:P1	FSR2
Trace 0f37	FSR2	R4:P2	3V3
Trace 0f37	FSR2	R22:P1	SCL
Trace 1cfe	FSR3	R20:P1	None
Trace 1cfe	FSR3	R20:P2	None
Trace 0464	FSR3	D1:CATHODE_2	None
Trace 56bf	FSR4	SW1:1-1	None
Trace 4894	FSR4	R2:P2	SCL
D2:A	GND	Trace 98cc	3V3
D4:GND	GND	C5:P1	FSR4
D4:GND	GND	C5:P2	None
D4:VCC	GND	C5:P2	None
U1:GND	GND	U1:GND	None
R22:P1	SCL	Trace 8f9b	FSR3
R22:P1	SCL	Trace 4435	FSR3
Trace 1257	SCL	J3:2	SDA
Trace 1257	SCL	Trace 6d8c	SDA
Trace 1257	SCL	J3:3	None
Trace e9f5	SCL	J3:2	SDA
Trace e9f5	SCL	J3:3	None
Trace e9f5	SCL	SW1:Pad	None
Trace e9f5	SCL	SW1:Pad	None
R23:P1	SDA	SW1:2	GND
Trace 6d8c	SDA	Trace e9f5	SCL
Trace 6d8c	SDA	J3:3	None
Trace 6d8c	SDA	J3:4	None
Trace a513	SDA	SW1:1	EN
Trace a513	SDA	SW1:2	GND
Trace a513	SDA	Trace e9f5	SCL
Trace a513	SDA	J3:3	None
Trace a513	SDA	J3:4	None
D1:CATHODE_2	None	Trace 52e1	FSR3
D1:CATHODE_3	None	Trace 52e1	FSR3
D3:A	None	Trace 9cf2	FSR1
D3:K	None	Trace 9cf2	FSR1
D4:GND	None	Trace 3e87	3V3
J2:Pin_1	None	Trace dcd8	FSR1
J2:Pin_1	None	Trace a513	SDA
J2:Pin_2	None	Trace a513	SDA
R8:P1	None	Trace 8f9b	FSR3
R8:P2	None	Trace 8f9b	FSR3
R10:P2	None	Trace 0f37	FSR2
R10:P2	None	R22:P1	SCL
R20:P2	None	Trace fc20	FSR1
R22:P2	None	Trace d1b2	SCL
SW1:1-1	None	Trace c44e	FSR4
SW1:2-1	None	J2:Pin_4	FSR2
SW1:2-1	None	Trace c44e	FSR4

Invalid Layer

Reports nodes that are assigned to a layer that doesn't exist in the layout stackup.

Component Overrides

Reports components that have been modified using the "!important" flag.

Airwires

Reports missing routed traces between pads in a net.

Layers with Multiple Fills

Reports layers that have multiple copper fills of different nets. Make sure the Connected Layers rule value of nets with fills is valid.

Floating Copper

Detect any via, trace or copper fill island that is not connected to any net.

Protected Intrusions

Reports intrusions from objects of other nets into polygons or fills that have the Protected layout rule applied.

Manufacturing

Manufacturer Part Number • 13

	Designator	MPN
	D2	None
	D3	None
	R1	None
	R2	None
	R4	None
	R13	None
	R16	None
	R17	None
	R18	None
	R19	None
	R19	None
	R20	None
	R20	None

Parts Available

Beta

Checks that all components are available from distributors.

System Checks

Auto-Layout

Beta

Reports issues with Auto-Layout if Flux cannot route something or must ignore a configuration.

Passive Components

Resistor Power Rating

Beta

Checks that the power traveling across a given resistor is under its rating with 50% headroom.

Learn more

Pull Up/Pull Down Presence

Beta

Checks that IC pins that require pull up or pull down resistors have them.

Learn more

Capacitor Voltage Rating

Beta

Checks that capacitors have appropriate voltage ratings to prevent overheating and ensure reliable circuit operation.

Ground
A common return path for electric current. Commonly known as ground.
jharwinbarrozo
20.5M
Net Portal
Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
jharwinbarrozo
43.0M
Power Net Portal
Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
jharwinbarrozo
11.4M
Generic Resistor
A generic fixed resistor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard resistor values: 1.0Ω 10Ω 100Ω 1.0kΩ 10kΩ 100kΩ 1.0MΩ 1.1Ω 11Ω 110Ω 1.1kΩ 11kΩ 110kΩ 1.1MΩ 1.2Ω 12Ω 120Ω 1.2kΩ 12kΩ 120kΩ 1.2MΩ 1.3Ω 13Ω 130Ω 1.3kΩ 13kΩ 130kΩ 1.3MΩ 1.5Ω 15Ω 150Ω 1.5kΩ 15kΩ 150kΩ 1.5MΩ 1.6Ω 16Ω 160Ω 1.6kΩ 16kΩ 160kΩ 1.6MΩ 1.8Ω 18Ω 180Ω 1.8KΩ 18kΩ 180kΩ 1.8MΩ 2.0Ω 20Ω 200Ω 2.0kΩ 20kΩ 200kΩ 2.0MΩ 2.2Ω 22Ω 220Ω 2.2kΩ 22kΩ 220kΩ 2.2MΩ 2.4Ω 24Ω 240Ω 2.4kΩ 24kΩ 240kΩ 2.4MΩ 2.7Ω 27Ω 270Ω 2.7kΩ 27kΩ 270kΩ 2.7MΩ 3.0Ω 30Ω 300Ω 3.0KΩ 30KΩ 300KΩ 3.0MΩ 3.3Ω 33Ω 330Ω 3.3kΩ 33kΩ 330kΩ 3.3MΩ 3.6Ω 36Ω 360Ω 3.6kΩ 36kΩ 360kΩ 3.6MΩ 3.9Ω 39Ω 390Ω 3.9kΩ 39kΩ 390kΩ 3.9MΩ 4.3Ω 43Ω 430Ω 4.3kΩ 43KΩ 430KΩ 4.3MΩ 4.7Ω 47Ω 470Ω 4.7kΩ 47kΩ 470kΩ 4.7MΩ 5.1Ω 51Ω 510Ω 5.1kΩ 51kΩ 510kΩ 5.1MΩ 5.6Ω 56Ω 560Ω 5.6kΩ 56kΩ 560kΩ 5.6MΩ 6.2Ω 62Ω 620Ω 6.2kΩ 62KΩ 620KΩ 6.2MΩ 6.8Ω 68Ω 680Ω 6.8kΩ 68kΩ 680kΩ 6.8MΩ 7.5Ω 75Ω 750Ω 7.5kΩ 75kΩ 750kΩ 7.5MΩ 8.2Ω 82Ω 820Ω 8.2kΩ 82kΩ 820kΩ 8.2MΩ 9.1Ω 91Ω 910Ω 9.1kΩ 91kΩ 910kΩ 9.1MΩ #generics #CommonPartsLibrary
jharwinbarrozo
1.5M
Generic Capacitor
A generic fixed capacitor ideal for rapid circuit topology development. You can choose between polarized and non-polarized types, its symbol and the footprint will automatically adapt based on your selection. Supported options include standard SMD sizes for ceramic capacitors (e.g., 0402, 0603, 0805), SMD sizes for aluminum electrolytic capacitors, and through-hole footprints for polarized capacitors. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard capacitor values: 1.0pF 10pF 100pF 1000pF 0.01uF 0.1uF 1.0uF 10uF 100uF 1000uF 10,000uF 1.1pF 11pF 110pF 1100pF 1.2pF 12pF 120pF 1200pF 1.3pF 13pF 130pF 1300pF 1.5pF 15pF 150pF 1500pF 0.015uF 0.15uF 1.5uF 15uF 150uF 1500uF 1.6pF 16pF 160pF 1600pF 1.8pF 18pF 180pF 1800pF 2.0pF 20pF 200pF 2000pF 2.2pF 22pF 20pF 2200pF 0.022uF 0.22uF 2.2uF 22uF 220uF 2200uF 2.4pF 24pF 240pF 2400pF 2.7pF 27pF 270pF 2700pF 3.0pF 30pF 300pF 3000pF 3.3pF 33pF 330pF 3300pF 0.033uF 0.33uF 3.3uF 33uF 330uF 3300uF 3.6pF 36pF 360pF 3600pF 3.9pF 39pF 390pF 3900pF 4.3pF 43pF 430pF 4300pF 4.7pF 47pF 470pF 4700pF 0.047uF 0.47uF 4.7uF 47uF 470uF 4700uF 5.1pF 51pF 510pF 5100pF 5.6pF 56pF 560pF 5600pF 6.2pF 62pF 620pF 6200pF 6.8pF 68pF 680pF 6800pF 0.068uF 0.68uF 6.8uF 68uF 680uF 6800uF 7.5pF 75pF 750pF 7500pF 8.2pF 82pF 820pF 8200pF 9.1pF 91pF 910pF 9100pF #generics #CommonPartsLibrary
jharwinbarrozo
1.5M
Generic Inductor
A generic fixed inductor for rapid developing circuit topology. *You can now change the footprint and 3D model at the top level anytime you want. This is the power of #generics
jharwinbarrozo
15.1k
Terminal
An electrical connector acting as reusable interface to a conductor and creating a point where external circuits can be connected.
natarius
RMCF0805JT47K0
47 kOhms ±5% 0.125W, 1/8W Chip Resistor 0805 (2012 Metric) Automotive AEC-Q200 Thick Film #forLedBlink
jharwinbarrozo
1.2M
875105359001
10uF Capacitor Aluminum Polymer 20% 16V SMD 5x5.3mm #forLedBlink #commonpartslibrary #capacitor #aluminumpolymer #radialcan
jharwinbarrozo
1.2M
CTL1206FYW1T
Yellow 595nm LED Indication - Discrete 1.7V 1206 (3216 Metric) #forLedBlink
jharwinbarrozo
1.1M

Inspect

Brainstorm a new project with AI [Example]

Controls

Properties

Board Size

DRC Issues

BOM (qty-100 LCSC)

System Architecture

Power Source

Target Use Case

Primary MCU

Sensor Suite

Radio Interfaces

ERC Issues

Project Name

GPIO Pin Map

Draft ESP32-C3-WROOM-02(-U) GPIO assignment (updated):
Power / Reset / Boot
- EN (CHIP_EN):
  - Function: Manual reset input (active high enable)
  - Net: EN
  - External: Connected to SW1 (momentary reset button), TP_EN test pad, and pull-up to 3V3 per ESP32-C3 ref design
- IO0:
  - Function: PROG_BOOT / strapping pin
  - Net: PROG_BOOT
  - Use: BOOT0 for entering UART download mode when held low during reset
  - External: Connected to TP_BOOT test pad and weak pull-up R21 to 3V3
  - Notes: Do not heavily load; only use for boot/flash circuitry and optional weak pull-ups/downs

UART Programming Interface
- IO20 (RXD):
  - Signal: PROG_RX
  - Net: PROG_RX
  - Function: UART0 RX for programming/logging
  - External: Routed to TP_PROG_RX test pad (off-board USB-UART bridge)
- IO21 (TXD):
  - Signal: PROG_TX
  - Net: PROG_TX
  - Function: UART0 TX for programming/logging
  - External: Routed to TP_PROG_TX test pad (off-board USB-UART bridge)

I2C Bus (IMU + External I2C Connector J3)
- IO4 (GPIO4):
  - Signal: SCL
  - Net: SCL
  - Function: I2C SCL (MPU-6050 U3 + JST-PH I2C connector J3 pin 1)
  - External: Pulled up to 3V3 via R1/R22 located near U1
- IO5 (GPIO5):
  - Signal: SDA
  - Net: SDA
  - Function: I2C SDA (MPU-6050 U3 + JST-PH I2C connector J3 pin 2)
  - External: Pulled up to 3V3 via R2/R23 located near U1

FSR Analog Inputs (from 6-pin JST-PH FSR Harness J2)
- IO1 (ADC1_CH1) – FSR1:
  - Net: FSR1
  - Function: Analog input for FSR channel 1
  - External: J2 Pin_3 via resistor network R13/R7 and C6
- IO4/IO5 no longer used as analog inputs (dedicated to I2C)
- IO6 (ADC1_CH6) – FSR4 / LED_PWR (current rev):
  - Net: FSR4 / LED_PWR shared
  - Function: Analog input for FSR channel 4 and drive for power LED (through R17)
  - Notes: Shared analog/digital usage; to be separated in next revision
- IO7 – LED_STATUS:
  - Net: LED_STATUS
  - Function: Status LED D3 (through R18)

Other Boot/Strap Pins (Reserved / Not Used for External Connectors)
- IO2:
  - Bootstrapped; kept on-board only with simple pulls as per Espressif guidelines; not exported to connectors

USB-C / Power Path
- J1: 124018312112A USB-C receptacle
  - VBUS_A/VBUS_B:
    - Function: 5V input from host
    - Net: VBUS
    - Path: J1 VBUS pins → TVS D4 (PRTR5V0U2X,215) VCC/GND → U4 NCP176 IN → 3V3 rail
  - CC1/CC2:
    - Nets: CC1, CC2
    - Function: USB-C attach detection (power sink)
    - External: Each tied to GND via 5.1 kΩ Rd resistors R19 (CC1) and R20 (CC2)
  - D+/D-:
    - Nets: D1+/D1-, D2+/D2-
    - Function: ESD-protected only via D1 (SMF05C.TCT); not connected to ESP32 USB

Power / Ground
- 3V3:
  - Net: 3V3
  - Source: U4 NCP176BMX330TCG regulator (from USB VBUS)
  - Sinks: U1/U2 3V3, I2C pull-ups (R1/R2/R22/R23), LED resistors (R17/R18), FSR divider top nodes, IMU U3 supply and decoupling, etc.
- GND:
  - Net: GND
  - Common reference for ESP32, IMU, USB-C shield/grounds, FSR dividers, LEDs, and TVS diodes

Programming Test Access
- PROG_TX: TP_PROG_TX net portal tied to U1:TXD
- PROG_RX: TP_PROG_RX net portal tied to U1:RXD
- BOOT: TP_BOOT net portal tied to U1:IO0 (PROG_BOOT net)
- EN: TP_EN net portal tied to U1:EN (EN net)

Antenna Keep-Out (ESP32-C3-WROOM-02/02U)
- Requirement (schematic note only in this rev):
  - Keep copper, vias, components, and high-profile objects out of the antenna region defined in the ESP32-C3-WROOM-02/-02U datasheet (typically the antenna end of the module plus a clearance region extending off-board edge).
  - Place ESP32-C3 module at PCB edge with antenna end extending beyond or flush with board outline.
  - Mark keep-out on silkscreen and mechanical layers in layout (to be implemented during PCB layout).

USB-C Power-Only Mode Summary
- Port Type: USB-C sink, power-only
- CC1/CC2: 5.1 kΩ Rd to GND (R19/R20)
- VBUS: Routed only to TVS D4 and LDO U4 IN, not shorted to GND
- Data Lines: Protected by D1 but not connected to ESP32.

ERC / DRC Tracking
- ERC Issues: See latest @review output (all critical errors resolved for USB-C, I2C remap, EN/BOOT/test pads, and IMU strapping)
- DRC Issues: []

Board and Manufacturing
- Board Size: 80.0 mm × 60.0 mm
- Power Requirements: USB
- Power Source: USB-C 5V from host
- Manufacturing Quantity Target: 100
- BOM (qty-100 LCSC: Compiled BOM with LCSC pricing for 100 units

External Interfaces

Availability & Pricing

Distributor		Qty 1

Assets

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Brainstorm w Copilot.png

id=Brainstorm w Copilot

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