The workaround executor has settled. I’m reconciling its exact retained/reverted result against a fresh live DRC and targeted-routing canary now; I’ll continue only from the verified state.
I filed an updated engineering escalation containing the serialized field, node counts, commits, reproduction steps, and failed workarounds.
Practical paths forward
Use explicit copper primitives for each remaining connection; this bypasses the targeted router but is effectively manual routing.
Export the design to KiCad or another EDA tool and complete placement/routing there.
Wait for Flux to correct the backend layer importer, then resume targeted routing here.
Given the repeated failures and the unresolved VCAP/SDRAM placement redesign, exporting to KiCad is currently the lowest-risk path to completing this board. Flux support can be reached at https://docs.flux.ai/Introduction/getting-support.
Placement cleanup was completed on the approved custom board without changing the outline or stackup. No traces were routed.
Components placed: 166 / 166
Top-side components: 159
Bottom-side components: 7
Placement-linter overlaps: 0
Placement-linter out-of-bounds: 0
Placement-linter keepout violations: 0
ODB++ distinct-component pad overlaps: 0 top, 0 bottom
ODB++ component origins outside board: 0
ODB++ component pad geometries outside board: 0
Board outline
Overall dimensions: 76.0 mm × 120.0 mm
Shape: custom vertical handheld outline
Upper corners: modest rounded transitions, approximately 4 mm
Lower corners: larger rounded transitions, approximately 12 mm, producing the approved rounded lower body
Parsed ODB++ board area: 9064.96 mm²
Outline unchanged during this cleanup
Stackup
Custom production-oriented 6-copper-layer, approximately 1.48 mm total thickness:
L1 Top Copper — Signal, 35 µm
L2 Mid-Layer 1 — Ground Plane, 35 µm
L3 Mid-Layer 2 — Signal, 35 µm
L4 Mid-Layer 3 — Power Plane, 35 µm
L5 Mid-Layer 4 — Ground Plane, 35 µm
L6 Bottom Copper — Signal, 35 µm
The two continuous ground-reference layers remain L2 and L5; L4 remains the power plane.
Connector and mechanical edge assignments
Coordinates below are component origins in board-centered millimeters.
Table
Ref
Function
Assignment
Origin / rotation
J1
USB-C USB2 device/sink
Bottom edge, centered
(0.0, -57.95), 0°
J2
External music-library microSD
Right edge, externally accessible
(20.7, 2.0), 90°
J3
Display FPC, bottom-contact ZIF
Upper-front/top-center
(0.0, 54.3), 0°
J4
3.5 mm headphone output
Left edge, upper of the two audio jacks
(-28.0, -1.0), 270°
J5
3.5 mm fixed line output
Left edge, separated about 21 mm below J4
(-31.4, -22.0), 270°
J6
Serviceable LiPo connector
Upper-left internal/service edge
(-32.2, 42.0), 270°
J7
SWD/service header
Top-left service region
(-32.0, 54.0), 0°
J8
Internal system/Rockbox microSD
Upper-right internal/service edge
(20.7, 45.0), 90°
Project-local edge-placement datum overrides were applied so the connector bodies remain fully in bounds while their intended mating/card insertion datums align to the outline:
J2/J8 edge-placement offset: 17.3 mm
J6 edge-placement offset: 5.8 mm
Fresh Edge Placement DRC reports these three edge issues resolved.
Bottom-side components
Only low-profile passives were moved to the bottom; no user connector, switch, IC, or tall/mechanical component is on the bottom.
C61 — STM32 local 3V3 bulk
C54 — codec-area passive
C71 — internal microSD high-frequency bypass
C57 — audio-area passive
R15 — headphone-coupled audio resistor
C72 — internal microSD bulk
C24 — SDRAM VDD/VDDQ decoupling
Placement cleanup performed
Cleared the previous placement collisions by moving small passives and support parts rather than disturbing the STM32H743/SDRAM core geometry.
Reorganized external microSD pull-ups R24–R28 into a compact bank beside J2.
Moved D2 and D5 to clean ESD locations near their respective microSD interfaces without blocking connector or IC pad escape.
Moved D1 away from the USB-C body while retaining bottom-edge USB protection proximity.
Kept USB3320/ULPI, STM32H743/SDRAM, display, power-converter, audio, and service-interface functional group locations intact.
Preserved top-side placement for all mechanical/user interfaces.
Mechanical clearance review
The J3 display FPC remains in the upper-front region with its existing bottom-contact/insertion orientation preserved.
The lower-front region remains free of tall central mechanical components; the cassette-related switches/encoder stay toward the lower side regions, with J1 at the bottom edge.
No tall bottom-side parts were introduced beneath the intended rear/central battery area.
The seven bottom parts are low-profile passives, but the exact pouch-pack outline, compression foam, adhesive, and enclosure ribs are not represented as a formal 3D keepout. A battery-envelope keepout should be added when final pack dimensions are selected.
The future six-pogo/magnet module mechanics are still not represented by a formal layout keepout; the placement preserves the intended clear zone, but the final cassette drawing should be converted into a locked mechanical keepout before routing/mechanical release.
JP1: 2 errors — terminals A and B overlap the shared 13 solder-jumper land while carrying different nets.
U4: 5 errors — GND exposed pad EP overlaps five unconnected helper/thermal pads.
The fresh auto-route feasibility check condenses these into 4 blocking anomaly groups:
J4 SH2 vs SHIELDING
J4 SH1 vs SHIELDING
JP1 13 vs A/B
U4 EP vs five unconnected helper pads
One advisory remains: the USB3320 exposed pad requires via-at-SMD handling.
These intrinsic footprint/net-model issues must be corrected in the affected parts or by safe project-local footprint/net overrides before auto-routing. Moving the components cannot resolve them.
Routing readiness
ROUTING READINESS: FAIL
The component placement itself is clean and placement-ready, but the current auto-route board check is blocked by the four intrinsic footprint-terminal anomaly groups above. No routing was performed.