3.3V 레귤레이터 추가 안내
Thought for 1 min 14 sec
검토용 회로도 PDF를 내보냈습니다.
원하시면 이어서 외주 검토용으로 같이 보낼 수 있게
- BOM CSV
- 검토 요청 메일 초안
- 현재 남은 ERC/DRC 요약 1페이지 도 바로 정리해드릴게요.
회로도에 결선이나 컴퍼넌트 정보가 없습니다.
Thought for 23 sec
맞습니다. 제가 드린 PDF는 검토용 회로도 PDF가 아니었습니다.
Flux 문서에서 가장 직접적인 답은 이겁니다:
Can I export my schematic as a PDF?No, you cannot export a PDF of your schematic from Flux right now.
그리고 Flux의 export는 데이터 포터빌리티/제조 중심 기능으로 안내되며, 협업은 보통 Flux 내부 공유를 권장합니다. 또한 현재 export 도구 안내상 내보내기 형식들은 PCB layout data 기준으로 생성되며 schematic export는 포함되지 않습니다
즉, 지금 보신 것처럼 결선이나 컴포넌트 정보가 없는 이유는 Flux에서 회로도 PDF export 자체를 지원하지 않기 때문입니다.
이전 답변은 제가 잘못 안내했습니다.
이전 답변은 제가 잘못 안내했습니다.
필요하시면 다음으로는:
- 외주 검토 요청용 문구를 정리해드리거나
- Flux에서 상대방이 프로젝트를 직접 보도록 공유하는 방식 기준으로 안내해드릴게요.
공유 방법 알려줘
U1부터 점검
ERC 문제 확인
BOM 정보 보기
Processor Evaluation Workflow Document
Purpose
This document defines the workflow for evaluating and selecting processors for the EV charger project. It is intended to guide a consistent down-selection process for both the real-time control board and the upper control board.
Scope
This workflow applies to:
- Real-time control board processor evaluation
- Upper control board processor evaluation
- Cross-board compatibility review
- Final processor freeze decision
Workflow Overview
- Define board-specific processor requirements and commercial constraints
- Build the shortlist of candidate families and devices
- Apply hard-gate elimination criteria including package assembly and lead-time viability
- Score remaining candidates using weighted technical, commercial, and assembly criteria
- Review cross-board architectural fit
- Assess implementation, sourcing, lead-time, cost, and assembly risks
- Select recommended candidate and backup candidate with explicit commercial and manufacturability positions
- Freeze processor choices after exit criteria are met
Phase 1: Requirements Baseline
Inputs
- Project requirements and architecture
- Real-time board I/O allocation
- Upper control board I/O allocation
- MCU selection requirements
- Processor comparison checklist
- MCU shortlist evaluation matrix
- Processor down-selection scoring sheet
Actions
- Confirm the processor role for each board
- Confirm required peripherals, timing, memory, and communications needs
- Confirm required safety, debug, reset, and update capabilities
- Confirm package, lifecycle, and supply-chain constraints
- Confirm target cost range, comparison quantity or annual volume basis, and cost sensitivity
- Confirm acceptable lead-time window and sourcing assumptions
- Confirm package assembly constraints such as pitch, package family preference, assembly capability, rework risk, and inspection limits
Outputs
- Frozen processor requirement baseline for each board
- List of unresolved assumptions affecting processor selection
- Defined cost, lead-time, and package assembly acceptance criteria for the evaluation team
Phase 2: Candidate Shortlisting
Actions
- Identify candidate processor families for the real-time board
- Identify candidate processor families for the upper board
- Ensure each candidate is realistic for package, availability, lead time, assembly flow, and development flow
- Exclude candidates that obviously violate architecture or board-level constraints
Outputs
- Real-time board shortlist
- Upper board shortlist
- Candidate metadata table including package, indicative cost, lead time, and assembly notes
Phase 3: Hard-Gate Screening
Hard-Gate Categories
- Required ADC/peripheral coverage
- Real-time control capability
- Required communication interfaces
- Required memory minimums
- Debug/programming support
- Package and PCB feasibility
- Lifecycle and sourcing viability
- Lead-time acceptability
- Package assembly acceptability
Actions
- Mark each candidate pass/fail for hard-gate items
- Remove any candidate failing a hard-gate requirement
- Record elimination reasons for traceability
- Explicitly fail candidates that cannot meet project package assembly capability or lead-time constraints unless approved as research-only references
Outputs
- Reduced shortlist with documented eliminations
Phase 4: Weighted Technical Scoring
Scoring Categories
- Real-time performance fit
- Analog and ADC fit
- Communications fit
- Memory and firmware growth margin
- Toolchain and platform fit
- Package and PCB implementation fit
- Availability and lifecycle fit
- Cost fit
- Lead-time fit
- Package assembly risk
- Sourcing risk
- Future growth and integration headroom
Actions
- Score each surviving candidate using the approved scoring sheet
- Record evidence supporting each score
- Identify categories with major uncertainty or missing evidence
- Score cost using an explicit quantity basis and note any price-break assumptions
- Score lead time using dated source evidence and note whether the source is distributor, manufacturer, or broker-derived
- Score package assembly risk using project assembly capability, board density expectations, escape complexity, and rework practicality
Outputs
- Ranked candidate list for each board
- Evidence-backed score table with technical, cost, lead-time, and assembly positions
Phase 5: Cross-Board System Fit Review
Actions
- Review whether the chosen real-time and upper-board processors create unnecessary integration risk
- Compare debug flows, programming flows, and firmware maintenance burden
- Confirm board-to-board communications support remains clean and practical
- Confirm processor choices do not create avoidable complexity in clocks, supplies, or PCB escape
Outputs
- Cross-board compatibility review notes
- List of system-level tradeoffs
Phase 6: Risk Review
Risk Categories
- Firmware implementation risk
- Analog measurement risk
- Timing/control risk
- Package and PCB risk
- Availability and lifecycle risk
- Cost risk
- Lead-time risk
- Package assembly risk
- Documentation/tooling risk
- Future feature expansion risk
Actions
- Identify top risks for each candidate
- Assign mitigation ideas where possible
- Compare primary candidate vs backup candidate
- Distinguish between acceptable risk, mitigated risk, and unresolved blocker for cost, lead time, and package assembly
Outputs
- Risk register for shortlisted candidates
- Primary and backup recommendation set
Phase 7: Recommendation and Down-Selection
Actions
- Select the preferred candidate for the real-time board
- Select the preferred candidate for the upper board
- Select at least one backup option for each board
- Record the reasons for recommendation
- Record the commercial position for each recommendation including cost, lead-time, and package assembly status
- Record any conditions required before final freeze
Outputs
- Recommendation summary
- Preferred and backup processor choices
- Open items to resolve before freeze
- Decision record that explicitly states cost fit, lead-time fit, and package assembly fit for each recommended candidate
Phase 8: Freeze Gate
Freeze Criteria
- All hard-gate checks passed
- Weighted scoring completed and reviewed
- Cross-board fit reviewed
- Major implementation risks understood
- Package and pin-count margin accepted
- Supply-chain and lifecycle reviewed
- Cost position accepted
- Lead-time position accepted
- Package assembly risk accepted
- No unresolved blocker remains for schematic capture
Actions
- Hold processor freeze review
- Approve processor selection for schematic entry
- Update project documentation if processor choices change the architecture
- Confirm that the evidence log, scoring sheet, and shortlist matrix are aligned on cost, lead time, and assembly conclusions
Outputs
- Frozen processor selection
- Processor freeze decision record
Recommended Working Artifacts
- Candidate shortlist table
- Hard-gate screening table
- Weighted scoring sheet
- Evidence log
- Risk register
- Recommendation summary
- Freeze decision checklist
- Commercial and assembly snapshot for each candidate
Review Roles
Suggested Review Participants
- System architect
- Hardware lead
- Firmware lead
- Compliance or certification reviewer
- Procurement or sourcing reviewer if available
Decision Rules
- Do not select a processor only because it is familiar if it fails key growth or integration needs
- Prefer candidates with evidence-backed fit over assumptions
- Keep at least one backup candidate until schematic capture is stable
- Avoid freezing processors before critical board-to-board and peripheral assumptions are stable
- Do not recommend a preferred candidate if cost, lead time, or package assembly risk remains unbounded without explicit acceptance by the project team
- Prefer candidates with dated sourcing evidence and clear assembly feasibility over candidates that only win on nominal technical score
Project-Specific Notes
- The real-time control board should prioritize deterministic control, measurement, safety inputs, and charging state-machine support
- The upper control board should prioritize communications, serviceability, update handling, and protocol growth
- Board-to-board interface decisions such as UART vs CAN can affect processor selection and should be resolved before final freeze
Exit Criteria
This workflow is complete when:
- A preferred and backup processor are identified for each board
- The scoring and risk review are documented
- Open questions affecting processor selection are either resolved or explicitly accepted
- Cost, lead-time, and package assembly positions are documented for the recommended candidates
- The project is ready to move from processor evaluation into detailed schematic capture
Purpose
Scope
Workflow Overview
Phase 1: Requirements Baseline
Inputs
Actions
Outputs
Phase 2: Candidate Shortlisting
Actions
Outputs
Phase 3: Hard-Gate Screening
Hard-Gate Categories
Actions
Outputs
Phase 4: Weighted Technical Scoring
Scoring Categories
Actions
Outputs
Phase 5: Cross-Board System Fit Review
Actions
Outputs
Phase 6: Risk Review
Risk Categories
Actions
Outputs
Phase 7: Recommendation and Down-Selection
Actions
Outputs
Phase 8: Freeze Gate
Freeze Criteria
Actions
Outputs
Recommended Working Artifacts
Review Roles
Suggested Review Participants
Decision Rules
Project-Specific Notes
Exit Criteria