3.3V 레귤레이터 추가 안내
Thought for 1 min 14 sec
검토용 회로도 PDF를 내보냈습니다.
원하시면 이어서 외주 검토용으로 같이 보낼 수 있게
- BOM CSV
- 검토 요청 메일 초안
- 현재 남은 ERC/DRC 요약 1페이지 도 바로 정리해드릴게요.
회로도에 결선이나 컴퍼넌트 정보가 없습니다.
Thought for 23 sec
맞습니다. 제가 드린 PDF는 검토용 회로도 PDF가 아니었습니다.
Flux 문서에서 가장 직접적인 답은 이겁니다:
Can I export my schematic as a PDF?No, you cannot export a PDF of your schematic from Flux right now.
그리고 Flux의 export는 데이터 포터빌리티/제조 중심 기능으로 안내되며, 협업은 보통 Flux 내부 공유를 권장합니다. 또한 현재 export 도구 안내상 내보내기 형식들은 PCB layout data 기준으로 생성되며 schematic export는 포함되지 않습니다
즉, 지금 보신 것처럼 결선이나 컴포넌트 정보가 없는 이유는 Flux에서 회로도 PDF export 자체를 지원하지 않기 때문입니다.
이전 답변은 제가 잘못 안내했습니다.
이전 답변은 제가 잘못 안내했습니다.
필요하시면 다음으로는:
- 외주 검토 요청용 문구를 정리해드리거나
- Flux에서 상대방이 프로젝트를 직접 보도록 공유하는 방식 기준으로 안내해드릴게요.
공유 방법 알려줘
U1부터 점검
ERC 문제 확인
BOM 정보 보기
Processor Down-Selection Scoring Sheet
Purpose
This document is the final scoring sheet used to down-select processor candidates for the EV charger project after initial screening and shortlist evaluation. It is intended to support a freeze decision for both:
- Real-time control board processor
- Upper control board processor
This sheet is used after the candidate set has already passed the high-level requirements and checklist stages.
How to Use This Sheet
- List each shortlisted processor candidate.
- Confirm that each candidate passes all hard-gate requirements.
- Score each candidate against the weighted criteria.
- Record evidence and risks for every score.
- Compare total weighted scores.
- Record the recommended winner, runner-up, and unresolved issues.
- Freeze only after package, package assembly risk, availability, lead time, toolchain, and architecture fit are confirmed.
Scoring Scale
Use the same scale for every category.
Table
| Score | Meaning |
|---|---|
| 0 | Unacceptable / fails requirement |
| 1 | Very weak |
| 2 | Weak / high risk |
| 3 | Acceptable |
| 4 | Strong |
| 5 | Excellent / best fit |
Weighted score = Raw score × Weight.
Section A: Real-Time Control Board Down-Selection
A1. Hard-Gate Checks
A candidate should normally not proceed if any hard-gate item fails.
Table
| Candidate | ADC fit | Timer/PWM fit | Interrupt latency fit | Safety I/O fit | Required comms fit | Debug/programming fit | Package feasible | Package assembly acceptable | Lifecycle acceptable | Lead time acceptable | Status |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Candidate 1 | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Proceed / Stop |
| Candidate 2 | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Proceed / Stop |
| Candidate 3 | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Proceed / Stop |
A2. Weighted Scoring Criteria
Table
| Category | Weight | What to Score |
|---|---|---|
| Real-time determinism | 10 | Timer quality, interrupt handling, predictable control behavior |
| ADC and analog fit | 10 | Channel count, performance, sampling flexibility, analog integration |
| Safety and fault handling fit | 10 | GPIO ownership, comparator/watchdog/reset support, fault isolation suitability |
| CP/PP and measurement timing support | 8 | PWM/ADC synchronization, capture/compare usefulness |
| Communications fit | 7 | UART/CAN/SPI/I2C support and flexibility |
| Firmware platform/toolchain fit | 7 | SDK quality, debugger support, team familiarity |
| Memory margin | 6 | Flash/RAM headroom for present and future firmware |
| Package and PCB risk | 5 | Pin count headroom, routing feasibility, PCB manufacturability |
| Package assembly risk | 4 | Assembly process fit, pitch/package handling risk, special process burden |
| Power and clocking fit | 5 | Clock options, reset behavior, brownout robustness |
| Availability/lifecycle risk | 6 | Supply continuity, lifecycle status, sourcing resilience |
| Lead time fit | 4 | Current lead time position versus project schedule and sourcing flexibility |
| Cost fit | 5 | Relative production cost at project volume |
| Growth headroom | 8 | Margin for future protection, diagnostics, and protocol growth |
A3. Real-Time Board Candidate Scoring Table
Table
| Candidate | RT Determinism (10) | ADC/Analog (10) | Safety/Fault (10) | CP/PP Timing (8) | Comms (7) | Toolchain (7) | Memory (6) | Package (5) | Assembly Risk (4) | Power/Clock (5) | Availability (6) | Lead Time (4) | Cost (5) | Growth (8) | Total |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Candidate 1 | |||||||||||||||
| Candidate 2 | |||||||||||||||
| Candidate 3 |
A4. Real-Time Board Evidence / Notes
Table
| Candidate | Strengths | Weaknesses | Major Risks | Cost / Lead Time Position | Package Assembly Risk Notes | Open Questions | Recommendation |
|---|---|---|---|---|---|---|---|
| Candidate 1 | |||||||
| Candidate 2 | |||||||
| Candidate 3 |
Section B: Upper Control Board Down-Selection
B1. Hard-Gate Checks
Table
| Candidate | Board-to-board comms fit | Ethernet/network fit | External interface fit | Storage/update fit | Debug/service fit | Package feasible | Package assembly acceptable | Lifecycle acceptable | Lead time acceptable | Status |
|---|---|---|---|---|---|---|---|---|---|---|
| Candidate 1 | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Proceed / Stop |
| Candidate 2 | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Proceed / Stop |
| Candidate 3 | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Pass/Fail | Proceed / Stop |
B2. Weighted Scoring Criteria
Table
| Category | Weight | What to Score |
|---|---|---|
| Communications/network fit | 10 | Ethernet, UART, CAN, RS-485, service/debug fit |
| Software platform fit | 10 | OS/firmware support, tools, maintainability |
| Memory and storage headroom | 9 | Flash/RAM/external storage support |
| Board-to-board integration fit | 8 | Clean interface to real-time board |
| Security/update support | 8 | Boot/update features, integrity support |
| Logging/data handling fit | 6 | Local logs, buffering, file/storage support |
| Package and PCB risk | 5 | Escape/routing risk, pin headroom |
| Package assembly risk | 4 | Assembly process fit, package handling risk, special process burden |
| Availability/lifecycle risk | 6 | Sourcing, longevity, product continuity |
| Lead time fit | 4 | Current lead time position versus schedule and sourcing flexibility |
| Cost fit | 5 | Relative unit cost and BOM impact |
| Growth headroom | 8 | Future protocol and service expansion |
| Debug/serviceability | 6 | Bring-up and field diagnostics fit |
| Power management fit | 6 | Rail compatibility, startup/reset behavior |
B3. Upper Board Candidate Scoring Table
Table
| Candidate | Comms/Network (10) | Software Platform (10) | Memory/Storage (9) | B2B Fit (8) | Security/Update (8) | Logging (6) | Package (5) | Assembly Risk (4) | Availability (6) | Lead Time (4) | Cost (5) | Growth (8) | Debug (6) | Power Mgmt (6) | Total |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Candidate 1 | |||||||||||||||
| Candidate 2 | |||||||||||||||
| Candidate 3 |
B4. Upper Board Evidence / Notes
Table
| Candidate | Strengths | Weaknesses | Major Risks | Cost / Lead Time Position | Package Assembly Risk Notes | Open Questions | Recommendation |
|---|---|---|---|---|---|---|---|
| Candidate 1 | |||||||
| Candidate 2 | |||||||
| Candidate 3 |
Section C: Cross-Board Decision Summary
Table
| Item | Real-Time Board | Upper Board |
|---|---|---|
| Selected candidate | ||
| Runner-up candidate | ||
| Reason for selection | ||
| Key risk remaining | ||
| Mitigation before freeze | ||
| Freeze ready | Yes / No | Yes / No |
Section D: Final Down-Selection Gate
Before freezing the processor choice, confirm all items below.
Table
| Gate Item | Real-Time Board | Upper Board | Notes |
|---|---|---|---|
| Candidate passes all hard-gate checks | Yes / No | Yes / No | |
| Package and pin-count margin confirmed | Yes / No | Yes / No | |
| Package assembly risk acceptable | Yes / No | Yes / No | |
| Toolchain and debug workflow confirmed | Yes / No | Yes / No | |
| Supply chain and lifecycle reviewed | Yes / No | Yes / No | |
| Lead time acceptable for project schedule | Yes / No | Yes / No | |
| Cost position acceptable for target volume | Yes / No | Yes / No | |
| Firmware growth margin acceptable | Yes / No | Yes / No | |
| Board-to-board interface fit confirmed | Yes / No | Yes / No | |
| No blocking open questions remain | Yes / No | Yes / No |
Section E: Project-Specific Open Questions
- Will the board-to-board channel freeze as UART first or CAN first?
- Will the upper control board require Ethernet at first revision or later?
- Is external memory needed on the upper board in the first revision?
- Does the real-time board require extra analog margin beyond the currently documented measurement set?
- Are there package constraints from enclosure, thermal, or isolation partitioning that reduce candidate options?
Exit Criteria
This sheet is complete when:
- Both boards have at least one recommended processor candidate and one runner-up.
- All weighted scores are supported by written evidence.
- All hard-gate criteria are checked.
- Remaining risks are documented with mitigation steps.
- The selected processors are ready to enter detailed part selection and schematic capture.
Purpose
How to Use This Sheet
Scoring Scale
Section A: Real-Time Control Board Down-Selection
A1. Hard-Gate Checks
A2. Weighted Scoring Criteria
A3. Real-Time Board Candidate Scoring Table
A4. Real-Time Board Evidence / Notes
Section B: Upper Control Board Down-Selection
B1. Hard-Gate Checks
B2. Weighted Scoring Criteria
B3. Upper Board Candidate Scoring Table
B4. Upper Board Evidence / Notes
Section C: Cross-Board Decision Summary
Section D: Final Down-Selection Gate
Section E: Project-Specific Open Questions
Exit Criteria