# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** hiraeth - **Created:** 10/4/2024 - **Last Updated:** 10/4/2024 - **Visibility:** Public - **Forks:** 1 ## Key Components ### ESP1 — [ESP32-C3-WROOM-02-N4](https://www.flux.ai/vasy_skral/esp32-c3-wroom-02-n4~tqi.md) - Manufacturer Name: Espressif Systems - Symbol Style: Parametric - Manufacturer Part Number: ESP32-C3-WROOM-02-N4 - License: https://creativecommons.org/licenses/by/4.0/ - Part Type: Module - Datasheet URL: https://www.espressif.com/sites/default/files/documentation/esp32-c3-wroom-02_datasheet_en.pdf **Pins:** - 3V3 [pin 1] - EN [pin 2] - GND [pin 38] - GND [pin 32] - GND [pin 37] - GND [pin 22] - GND [pin 19] - GND [pin 34] - GND [pin 31] - GND [pin 21] - GND [pin 39] - GND [pin 36] - GND [pin 9] - GND [pin 25] - GND [pin 33] - GND [pin 29] - GND [pin 30] - GND [pin 28] - GND [pin 20] - GND [pin 35] - GND [pin 26] - GND [pin 24] - GND [pin 23] - GND [pin 27] - IO0 [pin 18] - IO1 [pin 17] - IO10 [pin 10] - IO18 [pin 13] - IO19 [pin 14] - IO2 [pin 16] - IO3 [pin 15] - IO4 [pin 3] - IO5 [pin 4] - IO6 [pin 5] - IO7 [pin 6] - IO8 [pin 7] - IO9 [pin 8] - RXD [pin 11] - TXD [pin 12] ### U1 — [BMI270](https://www.flux.ai/jecstronic/bmi270~0q9.md) - Manufacturer Part Number: BMI270 - License: https://creativecommons.org/licenses/by/4.0/ - Datasheet URL: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmi270-ds000.pdf - Manufacturer Name: Bosch Sensortec - Part Type: Sensor **Pins:** - ASCX [pin 3] - ASDX [pin 2] - CSB [pin 12] - GND [pin 7] - GNDIO [pin 6] - INT1 [pin 4] - INT2 [pin 9] - OSCB [pin 10] - OSDO [pin 11] - SCX [pin 13] - SDO [pin 1] - SDX [pin 14] - VDD [pin 8] - VDDIO [pin 5] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/hiraeth/2-layer-jlcpcb-constraints~lr](https://www.flux.ai/hiraeth/2-layer-jlcpcb-constraints~lr).* --- *Generated from [https://www.flux.ai/hiraeth/2-layer-jlcpcb-constraints~lr](https://www.flux.ai/hiraeth/2-layer-jlcpcb-constraints~lr)*