U3 Pin Configuration Details
Thought for 2 mins 24 sec
Below is the full pin-out for U3 (ADE7953ACPZ) with each pin’s number, name, and primary function as described in the ADE7953 datasheet.
Table
| Pin No. | Pin Name | Function |
|---|---|---|
| 1 | ZX | Voltage-channel zero-crossing output |
| 2 | ~RESET | Active-low hardware reset input |
| 3 | VINTD | 2.5 V digital LDO output (decouple with 4.7 µF + 100 nF) |
| 4 | DGND | Digital ground |
| 5 | IAP | Current channel A positive ADC input |
| 6 | IAN | Current channel A negative ADC input |
| 7 | PULL_HIGH | Pull-up network connection for ADC inputs |
| 8 | PULL_HIGH | Secondary pull-up network for alternate functions |
| 9 | IBP | Current channel B positive ADC input |
| 10 | IBN | Current channel B negative ADC input |
| 11 | VN | Voltage channel negative ADC input |
| 12 | VP | Voltage channel positive ADC input |
| 13 | REF | ADC reference input |
| 14 | PULL_LOW | Pull-down network connection for ADC inputs |
| 15 | VINTA | 2.5 V analog LDO output (decouple per datasheet) |
| 16 | AGND | Analog ground |
| 17 | VDD | Digital supply (2.7 V–5.5 V) |
| 18 | CLKIN | Master clock input |
| 19 | CLKOUT | System clock output (divided clock) |
| 20 | ~REVP | Alternate output (e.g., phase-reversal indicator) |
| 21 | ZX_I | Current-channel zero-crossing output |
| 22 | ~IRQ | Interrupt output (active low) |
| 23 | CF1 | Frequency output 1 (energy-pulse output for channel A) |
| 24 | CF2 | Frequency output 2 (energy-pulse output for channel B) |
| 25 | SCLK | SPI serial clock |
| 26 | MISO/SDA/TX | SPI master-in/slave-out; I²C SDA; UART TX |
| 27 | MOSI/SCL/RX | SPI master-out/slave-in; I²C SCL; UART RX |
| 28 | ~CS | SPI chip-select (active low) |
| 29 | EP | Exposed pad (connect to AGND) |
Add VINTD cap
Add VINTA cap
Pull network values
EP pad connection
Rename SPI nets
copilot
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