Embryo Heartbeat Detector PCB Design

Thought for 5 sec

flux

I attempted the remaining routing fixes, but the board is still not DRC-clean.

Final live review:

Airwires: 10 errors remain
Dangling traces: 0 reported
Floating copper: 0 reported
Copper overlaps: 0 reported
Invalid layers: 0 reported
ERC warnings: 2 stale J1:0 USB-C floating-pin warnings remain

Main blockers:

AFE4404 BGA escape for ADC_RDY and TX1 / LED_K could not be routed by the available point-router.
USB-C duplicate D−/GND pad tie errors remain as physical airwires, although they are logically on the same schematic nets.
I removed exposed dangling/floating fragments; I did not export Gerbers.

Optical/sensor answers:

Q1. Is there an optical sensor in the project?
No actual optical emitter/photodiode part is present on the main board. The project has J3, a connector intended for an optical daughterboard, but no OSRAM SFH7050, SFH 4736, VEMD8080, or equivalent optical sensor is currently placed in the schematic.

Q2. What does J3 connect to?
Current J3 mapping:

J3 pin 1: 3V3 / sensor supply rail
J3 pin 2: LED_K → AFE4404 TX1
J3 pin 3: PD1_A → AFE4404 INP
J3 pin 4: AGND
J3 pin 5: PD2_A → AFE4404 INM
J3 pin 6: AGND

Q3. Do AFE4404 optical pins route to a connector/sensor?
Logically:

INP routes to J3 pin 3.
INM routes to J3 pin 5.
TX1 routes to J3 pin 2.
TX2 and TX3 are not used for the current connector path.

Physically, TX1 / LED_K still has an unresolved PCB airwire.

Q4. What needs to be added if no optical sensor exists?
Add a small optical daughterboard with an integrated sensor such as OSRAM SFH7050, or discrete IR LED + photodiode(s). For the current J3 wiring, use:

LED anode / sensor LED supply → J3 pin 1
LED cathode driven by AFE → J3 pin 2 / AFE TX1
Photodiode terminal 1 → J3 pin 3 / AFE INP
Photodiode terminal 2 → J3 pin 5 / AFE INM
Shield/analog return → J3 pins 4 and 6 / AGND

For SFH7050 specifically, verify the exact OSRAM package pinout before layout; the current 6-pin connector only supports one LED drive channel unless the daughterboard adds routing/muxing.

Q5. Which STM32 pin does ADC_RDY connect to?
AFE4404 ADC_RDY connects to STM32F303 PB0. PB0 is interrupt-capable via STM32 EXTI line 0, so firmware can trigger on the AFE data-ready edge.

Fix routing and sensor

Add optical daughterboard

Fix BGA fanout

Fix USB-C ties

Explain BGA escape

Review sensor path

Files

Schematic

Layout

3D View

Board Bring-Up Plan — OVA Pulse Embryo Heartbeat Detector

Current Fabrication Status

Do not order fabrication yet. The PCB is partially routed but not DRC-clean.

Latest validation state after cleanup routing:

Board: 60 mm x 50 mm rectangular, 4 copper layers.
Stackup intent: Top signal / Layer 2 GND / Layer 3 3.3 V power / Bottom signal.
Autorouting completed two passes.
Remaining blockers: 15 airwire errors and 5 dangling-trace warnings.
Manufacturing export was intentionally not generated because unrouted electrical connections remain.

Prerequisites

Equipment:

Current-limited bench supply or USB current meter
Digital multimeter
Oscilloscope, preferably 100 MHz or higher
ST-LINK or compatible SWD programmer
USB-C cable and host PC
Optical test fixture or known reflective target/egg mock-up

Safety notes:

USB VBUS input is 5 V nominal.
3.3 V rail is generated by AP2112K-3.3.
AFE4404 inputs and photodiode nodes are sensitive analog nodes; use ESD precautions.
Do not drive optical LED continuously at peak pulse current without firmware current/duty-cycle control.

1. Visual Inspection

Verify USB-C connector J1 solder joints and shell pads.
Verify AP2112K regulator U3 orientation.
Verify STM32F303RET6 U1 LQFP pin alignment and no bridges.
Verify AFE4404 U2 BGA placement/reflow quality.
Verify TFT connector J2, optical connector J3, and SWD header J4 orientation.
Check button and LED polarity/orientation.
Inspect 0402/0603 passives around U1 and U2 for tombstoning.

2. Power Rail Verification

Table

Rail	Source	Expected Voltage	Measure At	Current Limit	Pass Criteria
VBUS	USB-C J1	5.0 V	J1 VBUS / C1	100 mA first power-on	4.75–5.25 V, no overheating
3V3	AP2112K-3.3 U3	3.3 V	U3 VOUT / C2 / MCU VDD caps	100 mA first power-on, then 500 mA max USB budget	3.20–3.40 V
AFE supplies	3V3-derived AFE rails	3.3 V nominal	U2 decoupling caps C12–C16	100 mA first power-on	Stable, low ripple
TX_SUP / LED drive	AFE LED driver supply	3.3 V nominal	C16 and optical connector J3	Firmware-controlled pulses only	No continuous overcurrent

Procedure:

With no power, measure resistance from VBUS to GND and 3V3 to GND.
Apply USB power through a current-limited source.
Confirm 3V3 appears before connecting SWD/programmer.
Check AP2112K temperature under USB power.
Scope 3V3 near U1 and U2; excessive ripple or dips indicate layout/assembly issues.

3. Critical Signal Verification

Table

Signal	Net	Expected State	Measure At	Notes
Reset	NRST	High after reset RC delay	U1 NRST / J4 RST	Low pulse when reset asserted
Boot select	BOOT0	Low	U1 BOOT0	Ensures flash boot
SWD clock	SWCLK	Active during programming	J4 SWCLK	3.3 V logic
SWD data	SWDIO	Bidirectional during programming	J4 SWDIO	3.3 V logic
HSE clock	HSE_IN/HSE_OUT	8 MHz if firmware enables HSE	Y1/U1 pins	Optional clock source
LSE clock	LSE_IN/LSE_OUT	32.768 kHz if firmware enables LSE	Y2/U1 pins	RTC clock
AFE interrupt	AFE_ADC_RDY	Pulses when AFE conversions ready	U2 ADC_RDY / U1 PB0	Currently one routing blocker in layout review

4. Connector and Interface Tests

Table

Connector	Type	Pins/Signals	Test Method
J1	USB-C	VBUS, GND, D+, D-, CC1, CC2	USB power, continuity, USB enumeration
J4	SWD 1.27 mm	SWDIO, SWCLK, RST, GND	ST-LINK target detect
J3	6-pin optical	VLED, LED_K, PD1_A, PD1_K, PD2_A, AGND	Continuity to optical board; verify LED current path
J2	14-pin TFT FFC	SPI, control, backlight	TFT init and test pattern

5. Programming and Debug

Power from USB-C and confirm 3V3.
Connect ST-LINK to J4.
Use STM32CubeProgrammer to read device ID.
Program a minimal firmware image that toggles LED1/LED2 and prints USB CDC status.
Verify NRST and BOOT0 behavior if programming fails.

6. Functional Validation

Table

Test	Components	Expected Result
USB CDC enumeration	J1, D1, U1	Device enumerates on host
I2C scan	U1, U2, R9/R10 pull-ups	AFE4404 responds at configured address
AFE interrupt	U2 ADC_RDY to U1 PB0	Interrupt toggles during sampling
TFT display	U1, J2, Q1	Display initializes, backlight PWM works
Buttons	SW1, SW2, pull-ups	GPIO state changes on press
RGB/status LED	LED2, series resistors	Firmware can drive R/G/B channels
Optical LED pulse	U2, J3 optical LED path	LED pulses only under firmware control
Photodiode input	U2, J3 PD lines	AFE readings change with optical signal

7. Manufacturing Blockers to Resolve Before Ordering

Clear all remaining airwires.
Clear dangling-trace warnings.
Re-check USB D+/D- differential pair routing and length matching.
Verify AFE4404 BGA escape routing; the ADC_RDY net required a local fine-pitch exception.
Assign exact manufacturer part numbers for generic passives or approve generic BOM sourcing.
Re-run DRC/ERC until there are zero unresolved fabrication blockers.
Only then export Gerber, BOM, pick-and-place, and STEP/3D files.

Pass/Fail Summary

Table

Section	Result	Notes
Schematic functional blocks	Partial pass	Major blocks exist, but final datasheet signoff still recommended for AFE4404
PCB placement	Pass	Components fit in 60 mm x 50 mm outline
Routing	Fail	15 airwires remain after two autoroute passes
DRC	Fail	Dangling traces remain
Manufacturing readiness	Fail	Exports intentionally withheld

Board Status: Requires routing cleanup before fabrication.

Current Fabrication Status
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector and Interface Tests
5. Programming and Debug
6. Functional Validation
7. Manufacturing Blockers to Resolve Before Ordering
Pass/Fail Summary