PCB Net Routing Assistance

Diagnostic confirmed: the L2/L3 zones have copper geometry but are missing net assignments (effectiveNetId is null), so DRC treats them as decorative copper, not net-bound planes.

Fix in two steps:

STEP 1 — Create missing zones with explicit net assignment

The L2 GND zone and L3 3V0 dominant zone do not exist as proper queryable nodes. Create them now:

a) L2 GND PLANE

Layer: Mid-Layer 1 (L2)
Net: GND (assign explicitly — set effectiveNetId / net property)
Shape: circle, diameter 57.4mm, centred at (0, 0) — slightly smaller than the 58mm board outline to maintain 0.3mm edge clearance
Fill type: solid copper pour
Connection style: thermal relief to net-matching pads
Thermal relief: 4 spokes, 0.4mm spoke width, 0.3mm clearance
Stitching density: 2mm

b) L3 3V0 DOMINANT POUR

Layer: Mid-Layer 2 (L3)
Net: 3V0 (assign explicitly)
Shape: circle, diameter 57.4mm, centred at (0, 0), MINUS the two existing island regions (VSYS and 1V8_SGP41) — i.e., the 3V0 pour fills L3 everywhere EXCEPT inside the islands
Fill type: solid copper pour
Connection: thermal relief, same parameters as L2

STEP 2 — Assign net to existing islands

The L3 VSYS and L3 1V8_SGP41 island zones exist but have no net assignment. Set them now:

c) L3 VSYS ISLAND

Existing zone at (10, 18), 10×12mm
Net: VSYS (assign explicitly — currently has no effectiveNetId)

d) L3 1V8_SGP41 ISLAND

Existing zone at (-10, 22), 8×8mm
Net: 1V8_SGP41 (assign explicitly)

After Step 1 and Step 2:

Force a pour rebuild / fill regeneration on all 4 zones
Verify each zone now reports a valid effectiveNetId matching its intended net
Re-run DRC and report:
- New total airwire count
- Specifically the GND, 3V0, VSYS, 1V8_SGP41 airwire counts
- Render each layer (L1, L2, L3, L4) separately so I can verify the copper fills look correct

Expected result: airwire count should drop dramatically (from 170 to under 30), because most of the GND/3V0/VSYS airwires resolve through the now-net-bound planes.

If after this the count is still > 50, do NOT iterate further. Report back and stop. I'll handle the next decision from outside Flux.

Thought for 10 sec

flux

I’ll attempt the four-zone net binding exactly as specified, then verify DRC and layer rendering. First I’m checking whether the layout editor exposes net assignment for copper pours; if it does, I’ll apply the plane fixes and validate immediately.

Thought for 22 sec

flux

Blocked: I can’t complete this safely because the current layout controls do not expose any editable net/effectiveNetId/net-name property for zones. I verified that connectedLayers, shape, stitching, and thermal-style rules exist, but net, Net Name, and effectiveNetId are not valid editable zone rules.

I did not create more decorative copper, because that would repeat the same failure mode. The next decision needs to happen outside this interface: bind the copper pours to nets in the PCB editor/API, then rerun DRC and layer renders.

Find zone net UI

List airwires by net

Inspect zone properties

Export layout data

Refine this doc

Ask about this doc

Power Pin Membership Audit

Scope: refreshed after deleting stale U7/C19, re-adding fresh U7 SGP41-D-R4 and C19 1uF capacitor, and rewiring from scratch.

SGP41 filter topology

Intended topology is now restored in live schematic/net data:

Text
1V8_PRE -> R6 4.7 ohm -> 1V8_SGP41 -> U7 VDD
                                      -> C19 P1
C19 P2 -> GND
C12 P1 -> 1V8_PRE
C12 P2 -> GND
U7 VDDH -> 3V0
U7 SDA -> I2C_SDA
U7 SCL -> I2C_SCL
U7 VSS / EP / N/A -> GND

U7/C19 focused verification

Table

Node	Net membership	Expected	Status
U7 VDD	1V8_SGP41	1V8_SGP41 only	OK
C19 P1	1V8_SGP41	1V8_SGP41 only	OK
R6 P2	1V8_SGP41	1V8_SGP41	OK
U7 VDDH	3V0	3V0	OK
U7 SDA	I2C_SDA	I2C_SDA	OK
U7 SCL	I2C_SCL	I2C_SCL	OK
U7 VSS / EP / N/A	GND	GND	OK
C19 P2	GND	GND	OK

I2C bus verification

Table

Bus	Required participants	Observed participants	Status
I2C_SDA	U4 P0.26, U6 SDI, U7 SDA, J2 pin 2, R7 pull-up	U4, U6, U7, J2, R7	OK
I2C_SCL	U4 P0.27, U6 SCK, U7 SCL, J2 pin 3, R8 pull-up	U4, U6, U7, J2, R8	OK

Refreshed power-pin audit

Table

Component	Pin(s) checked	Net membership	Expected	Status
U1 nPM1100	VBUS B1/B2	VBUS_5V	VBUS_5V	OK
U1 nPM1100	VBAT D1/D2	BAT+	BAT+	OK
U1 nPM1100	VSYS C1/C2	VSYS	VSYS	OK
U1 nPM1100	VOUTB B5	3V0	3V0	OK
U1 nPM1100	AVSS C4/C5, PVSS A5	GND	GND	OK
U1 nPM1100	DEC A3/config pins	DEC	DEC	OK
U2 TPS61222	VIN	VSYS	VSYS	OK
U2 TPS61222	VOUT/FB	5V_SPS30	5V_SPS30	OK
U2 TPS61222	GND	GND	GND	OK
U3 XC6206P182	VIN	3V0	3V0	OK
U3 XC6206P182	VOUT	1V8_PRE	1V8_PRE	OK
U3 XC6206P182	VSS/GND	GND	GND	OK
U4 MDBT50Q	VDD	3V0	3V0	OK
U4 MDBT50Q	VDDH	3V0	3V0	OK
U4 MDBT50Q	VBUS	VBUS_5V	VBUS_5V	OK
U4 MDBT50Q	DCCH	MCU_DCCH	MCU_DCCH	OK
U4 MDBT50Q	GND pads	GND	GND	OK
U5 W25Q64JV	VCC	3V0	3V0	OK
U5 W25Q64JV	GND	GND	GND	OK
U6 BME280	VDD	3V0	3V0	OK
U6 BME280	VDDIO / CSB	3V0	3V0	OK
U6 BME280	GND pins	GND	GND	OK
U7 SGP41	VDD	1V8_SGP41	1V8_SGP41 only	OK
U7 SGP41	VDDH	3V0	3V0	OK
U7 SGP41	VSS / EP / N/A	GND	GND	OK
D1 USBLC6	VBUS	VBUS_5V	VBUS_5V	OK
D1 USBLC6	GND	GND	GND	OK
J1 USB-C	VBUS pins	VBUS_5V	VBUS_5V	OK
J1 USB-C	GND / shield pins	GND	GND	OK

ERC

ERC review after the re-add/re-wire shows 0 errors and 0 warnings.

Export/text check status

I exported the project netlist as nrf52840-wearable-power-tree.d356. Flux did not provide an EDIF export/readback path, and the available file reader failed to fetch the generated netlist URL for text inspection. Therefore I could not run the exact requested EDIF grep locally. Live schematic/net membership confirms the corrected U7 VDD membership.

SGP41 filter topology
U7/C19 focused verification
I2C bus verification
Refreshed power-pin audit
ERC
Export/text check status

Reviews

Documents

Firmware Starter — MDBT50Q-P1MV2 / nRF52840

Assembly Mechanical Integration

Pre-Route Layout Constraints

Power Pin Membership Audit

Haelo Clip v2 PCB Configuration

Haelo Clip v2 Auto-Placement Zones and Constraints

Haelo Clip v2 Board Features and Manufacturing Rules

Placement Review Fixes

Plane Audit and Airwire Report

Assets

Round LiPo placeholder 40mm diameter x 5mm with flying leads

round-lipo-40x5-placeholder.gltf3D Model

SPS30 placeholder 40.6x40.6x12.45mm mechanical model

sps30-placeholder.gltf3D Model

Project Name

nRF52840 Wearable Power Tree

Description

Battery-powered nRF52840 wearable power-tree schematic with USB-C charging, nPM1100 PMIC, 3V0, 1V8_SGP41, and 5V_SPS30 rails.

Properties

Implemen… Details

Haelo Clip v2 round-puck PCB: 58 mm circular outline centered at origin; Standard 4 Layer with L2 continuous GND plane, L3 power planes for 3V0/1V8_SGP41/VSYS; requested fabrication notes: 1.0 mm finished thickness, ENIG, matte black solder mask preferred with white silkscreen; matte white mask with black silkscreen acceptable if cheaper at JLCPCB.

Pricing & Availability

Distributor	Qty 1
Arrow	$10.02–$11.43
Digi-Key	$16.02–$20.31
HQonline	$8.71–$8.81
LCSC	$19.40–$20.49
Mouser	$17.72
TME	$8.03
Verical	$12.13–$17.73

Controls

New control

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haelolife / nRF52840 Wearable Power Tree

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