PCB Net Routing Assistance
Diagnostic confirmed: the L2/L3 zones have copper geometry but are
missing net assignments (effectiveNetId is null), so DRC treats them
as decorative copper, not net-bound planes.
Fix in two steps:
STEP 1 — Create missing zones with explicit net assignment
The L2 GND zone and L3 3V0 dominant zone do not exist as proper
queryable nodes. Create them now:
a) L2 GND PLANE
- Layer: Mid-Layer 1 (L2)
- Net: GND (assign explicitly — set effectiveNetId / net property)
- Shape: circle, diameter 57.4mm, centred at (0, 0) — slightly smaller than the 58mm board outline to maintain 0.3mm edge clearance
- Fill type: solid copper pour
- Connection style: thermal relief to net-matching pads
- Thermal relief: 4 spokes, 0.4mm spoke width, 0.3mm clearance
- Stitching density: 2mm
b) L3 3V0 DOMINANT POUR
- Layer: Mid-Layer 2 (L3)
- Net: 3V0 (assign explicitly)
- Shape: circle, diameter 57.4mm, centred at (0, 0), MINUS the two existing island regions (VSYS and 1V8_SGP41) — i.e., the 3V0 pour fills L3 everywhere EXCEPT inside the islands
- Fill type: solid copper pour
- Connection: thermal relief, same parameters as L2
STEP 2 — Assign net to existing islands
The L3 VSYS and L3 1V8_SGP41 island zones exist but have no net
assignment. Set them now:
c) L3 VSYS ISLAND
- Existing zone at (10, 18), 10×12mm
- Net: VSYS (assign explicitly — currently has no effectiveNetId)
d) L3 1V8_SGP41 ISLAND
- Existing zone at (-10, 22), 8×8mm
- Net: 1V8_SGP41 (assign explicitly)
After Step 1 and Step 2:
- Force a pour rebuild / fill regeneration on all 4 zones
- Verify each zone now reports a valid effectiveNetId matching its intended net
- Re-run DRC and report:
- New total airwire count
- Specifically the GND, 3V0, VSYS, 1V8_SGP41 airwire counts
- Render each layer (L1, L2, L3, L4) separately so I can verify the copper fills look correct
Expected result: airwire count should drop dramatically (from 170 to
under 30), because most of the GND/3V0/VSYS airwires resolve through
the now-net-bound planes.
If after this the count is still > 50, do NOT iterate further. Report
back and stop. I'll handle the next decision from outside Flux.
Thought for 10 sec
I’ll attempt the four-zone net binding exactly as specified, then verify DRC and layer rendering. First I’m checking whether the layout editor exposes net assignment for copper pours; if it does, I’ll apply the plane fixes and validate immediately.
Thought for 22 sec
Blocked: I can’t complete this safely because the current layout controls do not expose any editable net/effectiveNetId/net-name property for zones. I verified that
connectedLayers, shape, stitching, and thermal-style rules exist, but net, Net Name, and effectiveNetId are not valid editable zone rules.I did not create more decorative copper, because that would repeat the same failure mode. The next decision needs to happen outside this interface: bind the copper pours to nets in the PCB editor/API, then rerun DRC and layer renders.
Find zone net UI
List airwires by net
Inspect zone properties
Export layout data
Refine this doc
Ask about this doc
Haelo Clip v2 Board Features and Manufacturing Rules
Status: board-level features added; auto-placement has NOT been run.
Fiducials
Six global board-level fiducial pads were added:
Table
| Fiducial | Layer | Position | Copper | Solder mask opening |
|---|---|---|---|---|
| F1_TOP_GLOBAL_FID | L1 Top | (0, +25) | 1.0 mm circular | 3.0 mm nominal via 1.0 mm mask expansion |
| F2_TOP_GLOBAL_FID | L1 Top | (+22, -12) | 1.0 mm circular | 3.0 mm nominal via 1.0 mm mask expansion |
| F3_TOP_GLOBAL_FID | L1 Top | (-22, -12) | 1.0 mm circular | 3.0 mm nominal via 1.0 mm mask expansion |
| F1_BOTTOM_GLOBAL_FID | L4 Bottom | (0, +25) | 1.0 mm circular | 3.0 mm nominal via 1.0 mm mask expansion |
| F2_BOTTOM_GLOBAL_FID | L4 Bottom | (+22, -12) | 1.0 mm circular | 3.0 mm nominal via 1.0 mm mask expansion |
| F3_BOTTOM_GLOBAL_FID | L4 Bottom | (-22, -12) | 1.0 mm circular | 3.0 mm nominal via 1.0 mm mask expansion |
No silkscreen was placed over these fiducials.
GND stitching via ring
A board-level GND stitching via ring was added at approximately 26 mm radius using 0.3 mm drill / 0.6 mm pad STD pads with connectedLayers = All and direct connect.
Due to the three M2 mounting-hole keepouts, the ring intentionally leaves gaps around 12 o'clock, 4 o'clock, and 8 o'clock. Vias added:
GND_STITCH_000, 011, 022, 034, 045, 056, 068, 113, 124, 135, 146, 158, 169, 180, 191, 225, 236, 248, 259, 270, 281, 293, 304, 315, 349.
Count: 25 stitching vias.
Bring-up test pads
Board-level 1.0 mm SMT test pads were added on L1 and labeled with L1 silkscreen. These are engineering/dev-unit test aids and should be treated as DNP / not populated on production builds.
Table
| Test pad | Label | Intended net |
|---|---|---|
| TP_VBUS | VBUS_5V | VBUS_5V |
| TP_VSYS | VSYS | VSYS |
| TP_3V0 | 3V0 | 3V0 |
| TP_1V8 | 1V8 | 1V8_SGP41 |
| TP_5V_SPS30 | 5V_SPS30 | 5V_SPS30 |
| TP_BAT | BAT+ | BAT+ / cell voltage measurement |
| TP_BOOST_EN | BOOST_EN | BOOST_EN |
| TP_CHG | CHG | nPM1100 charge status |
| TP_GND_PWR | GND | GND near power zone |
| TP_GND_SENS | GND | GND near sensor zone |
Note: these were created as board-level pads, not schematic test-point components. If automatic net connectivity / BOM DNP reporting is required, convert these to schematic Test Point components before final manufacturing export.
Silkscreen branding and markings
Top/L1 silkscreen added:
- HAELO wordmark near LED area
- Clip v2.0 text
- U1 pin-1 dot
- U4 pin-1 plus mark
- J2 pin-1 mark
- USB insertion arrow
- A/K labels for D2, D3, D5, D6
- Test point labels
Bottom/L4 silkscreen added:
- HAELO Clip v2.0
- Rev A
- YYWW date-code placeholder
- Made in [TBD]
- AIR -> marker near SPS30 outline
- BAT+ and BAT- labels near battery pads, 1.5 mm text height
Manufacturing rules set
Rules applied:
- Layout boardInsetMargin = 0.2 mm (copper-to-edge intent)
- Layout keepOut = 0.25 mm (trace/object-to-edge intent)
- Global net minTraceWidth = 0.15 mm
- Global net keepOut = 0.15 mm (trace-to-trace intent)
- Power nets VBUS_5V, VSYS, 3V0, 1V8_SGP41, 5V_SPS30, BAT+ minTraceWidth = 0.30 mm where selector matching succeeded
- USB_D- minTraceWidth = 0.50 mm and keepOut = 0.20 mm were set; USB_D+ selector did not match via direct selector because of the plus sign syntax, so verify this specific rule before routing.
- Via ring pads use 0.30 mm drill / 0.60 mm pad.
Notes:
- Hole-to-edge 0.50 mm and drill-to-trace 0.20 mm are recorded here for DRC/manufacturing review; not all have a direct global rule representation in the current layout-rule interface.
- The requested USB rule has an internal conflict: earlier USB impedance target was trace width about 0.15 mm / gap about 0.20 mm for 90 ohm differential, while the manufacturing list says USB differential pair min width 0.50 mm. Recalculate impedance before routing and choose one requirement.
Copper-area balance estimate
Exact layer copper-area extraction is not available from the current layout summary, so these are estimates based on configured plane/fill features and current sparse routing state:
Table
| Layer | Estimated copper coverage | Comment |
|---|---|---|
| L1 Top | < 40% | Mostly pads, fiducials, stitching pads, sparse copper. Add GND fill in spare top areas after component placement. |
| L2 Ground Plane | ~100% less drill/keepout clearances | Continuous GND plane configured. |
| L3 Power Plane | ~50% to 55% | Three explicit power regions exist; remaining L3 can be copper-free or GND fill as planned. |
| L4 Bottom | < 40% | Battery pads, fiducials, sparse copper. Add GND fill in spare bottom areas after placement/routing, excluding the 38 mm rear battery keepout. |
Recommendation: after component placement and routing, add GND fill to spare L1 and L4 regions to improve copper balance and reduce reflow warpage, while preserving antenna, battery, and mechanical keepouts.
Fiducials
GND stitching via ring
Bring-up test pads
Silkscreen branding and markings
Manufacturing rules set
Copper-area balance estimate
