Circuit Review
Waiting for input
Table
| Item | Status | Independent finding |
|---|---|---|
| Bridge/fuse/MOV power path | Completed — pass | J1.1 → F1 → BR1 AC, with RV1 across the fused AC pair; J1.2 returns directly to the other bridge AC terminal. The MOV is downstream of the fuse. BR1+ feeds VRECT and BR1− feeds AGND. F1 is a 6.3 A time-lag device; RV1 is the 30 VAC S20K30 variant. |
| No VRECT reservoir capacitor | Completed — pass | VRECT connects only to BR1+, Q1 drain, R1 and TP1. C1 is 1 nF on VRECT_SCALED, not VRECT. No reservoir/bulk capacitor is present across VRECT–AGND. |
| AD633 equation and command scaling | Completed — pass | AD633 uses W = (X1−X2)(Y1−Y2)/10 V + Z. X1=VRECT_SCALED, X2=AGND, Y1=G_CMD_SCALED, Y2=AGND, Z=AGND. Divider ratios are 10 kΩ/(46.4 kΩ+46.4 kΩ+10 kΩ)=0.097276 and 9.31 kΩ/(24.9 kΩ+9.31 kΩ)=0.272143. At 3.3 V command, G_CMD_SCALED=0.8981 V; with 50 mΩ shunt this commands 5.723 Ω, or 100.64 W at 24 VAC nominal. D1 clamps the post-1 kΩ command node with cathode to DAC_CLAMPED and anode to AGND. |
| OPA197 feedback polarity | Completed — pass | OPA197 DBV pins are OUT=1, V−=2, IN+=3, IN−=4, V+=5. IREF is on IN+, Kelvin shunt voltage is on IN−, and increasing output increases MOSFET current/shunt voltage, giving negative feedback. |
| Compensation topology | Completed — topology pass; stability unresolved | R10=1 kΩ in series with C3=1 nF from LOOP_OUT to VSHUNT forms a series-RC high-frequency feedback path. R7=1 kΩ plus R8=100 Ω isolates/damps the MOSFET gate. This is electrically connected as intended, but the values are explicitly initial/placeholder values and were not proven stable with the actual MOSFET, wiring inductance and shunt layout. OPA197 literature supports output isolation for capacitive loading, but not this complete power-loop compensation without analysis. |
| Q1 D/S/G and gate clamp | Completed — pass | Q1 is now IXTH75N10L2. Manufacturer pinout is 1=Gate, 2=Drain, 3=Source, tab=Drain. Flux terminal/pad UIDs and pad numbers were checked before replacement, then Q1 was explicitly wired as pin 1→GATE, pin 2→VRECT, pin 3→VSHUNT. D2 remains cathode at GATE/anode at VSHUNT and R9 remains the gate-source pull-down. |
| Kelvin shunt sensing | Completed — schematic pass; PCB realization unresolved | RSH1=50 mΩ/5 W lies from VSHUNT to AGND. U2 IN− and the OC sense branch originate at VSHUNT. Logically correct, but a two-terminal generic resistor cannot guarantee true Kelvin copper; separate force/sense routing must be enforced in PCB layout. |
| TL431 bias | Completed — pass | U5 DBZ mapping K=1, REF=2, A=3 is correct. K and REF are tied, A is at AGND, and R11=6.2 kΩ from +15 V supplies about 2.017 mA. This exceeds the listed maximum minimum-regulation current of 0.7 mA, although that extracted numeric row was not machine-verified. |
| 6.5 A LM393 threshold | Completed — pass | R12=66.5 kΩ and R13=10 kΩ divide 2.495 V to 0.32614 V. Across 50 mΩ this is 6.523 A. R14/C6 provide a 10 µs input filter; C5 filters the threshold. |
| LM393 polarity and pull-up | Completed — pass | Comparator A pin 2 is inverting and pin 3 is non-inverting. OC_THRESHOLD is on pin 2 and VSHUNT_OC on pin 3, so overcurrent releases the open-collector output. R15=10 kΩ pulls OC_TRIP to +15 V, which forward-drives the fault-OR diode into FAULT_SET. Unused comparator B inputs are defined (AGND and REF_2V495), and its output is marked no-connect. |
| CD4013 set/reset and unused half | Completed — pass | SET and RESET are asynchronous active-high. FAULT_SET drives SET1; RESET_ENABLE drives RESET1; CLOCK1 and D1 are grounded. Q1 is FAULT_LATCH and ~Q1 is ENABLED. All four unused-half inputs SET2/D2/RESET2/CLOCK2 are grounded, as required for unused CMOS inputs. Unused Q2/~Q2 outputs are no-connect. |
| Startup default-off pulse | Completed — topology pass; startup margin unresolved | C7=100 nF from +15 V to FAULT_SET and R17=100 kΩ to AGND create an approximately 10 ms active-high SET pulse on rail rise. The topology defaults the latch to fault/off, but operation across arbitrary +15 V ramp rates, brownouts and rail sequencing is not guaranteed without transient validation or a supervisor. |
| Thermostat fail-safe | Completed — pass | J4.2=AGND; J4.1=THERM_FAULT. A normally closed thermostat holds THERM_FAULT low. Opening the contact lets R16=10 kΩ pull it to +15 V and D4 drives FAULT_SET high. This is fail-safe for open wire/contact, but not for a shorted thermostat/wire. |
| Q2 clamp polarity | Completed — pass | MMBT3904 pinout is B=1, E=2, C=3. E is at VSHUNT, C at GATE, and FAULT_LATCH drives B through 4.7 kΩ with 100 kΩ B-E pull-down. A latched fault therefore clamps gate to source. |
| Connector assignments | Completed — pass | J1: 1=fused AC leg, 2=AC return. J2: 1=+15 V, 2=AGND, 3=−15 V. J3: 1=0–3.3 V command, 2=AGND. J4: 1=thermostat sense, 2=AGND. J5: 1=FAULT_LATCH, 2=ENABLED, 3=AGND. J6: 1=+15 V, 2=RESET_ENABLE through an external momentary contact. |
| Decoupling | Completed — pass | AD633 and OPA197 each have 100 nF from +15 V to AGND and from AGND to −15 V. LM393 and CD4013 each have 100 nF +15 V decoupling. ±15 V rail entry has 22 µF bulk per rail. TL431/protection area has local 100 nF rail bypassing. |
| Fresh ERC and legibility checks | Completed — pass | Post-replacement review at 2026-09-11T06:25:18.285Z returned no WARNING, ERROR, UNCERTAIN, OPEN or USER findings for the selected Electrical Rule Checks and Schematic Legibility Checks. No violations required remediation. |
Overall result
Requested-item status
Mutations and blocked corrections
Unresolved engineering risks