Safety and Routing Verification Update — Neura Vital Patch
Date
2026-07-27
Safety Architecture Finalized in Schematic
- Added hardware USB-forced patient electrode disconnect interlock:
- Q1 = IRLML2502 N-MOSFET.
- R25 = 10 kΩ MCU series/current-limiting resistor from
MCU_PATIENT_SW_EN to PATIENT_SW_CTRL.
- R26 = 100 kΩ default pull-down on
PATIENT_SW_CTRL so switches are off during reset/high-Z MCU states.
- R27 = 100 kΩ USB_VBUS-to-gate resistor.
- R28 = 1 MΩ Q1 gate pull-down.
- Function: when
USB_VBUS is present, Q1 clamps PATIENT_SW_CTRL low and forces U11/U12/U13 patient/electrode analog switch controls to the disconnected state. MCU contention is limited by R25.
- Added RT1 = NTCSC0402E3103FLFT 10 kΩ NTC thermistor on BQ24074
TS.
- Removed R6 fixed 10 kΩ TS placeholder so the NTC is not corrupted by a parallel resistor.
Charger Values Finalized
- R4
ISET = 8.87 kΩ, giving ICHG ≈ 890 AΩ / 8.87 kΩ ≈ 100 mA.
- R3
ILIM = 8.06 kΩ, giving approximately 200 mA programmable input current limit if BQ24074 is configured for resistor-programmed input mode.
- Current EN state remains EN1=0, EN2=0 in schematic, corresponding to USB100 mode by the BQ24074 datasheet unless later control hardware/firmware changes this.
- R5
ITERM remains 10 kΩ pending selected LiPo capacity/vendor confirmation.
- RT1 must be placed in thermal contact with the LiPo cell or the battery pack must be changed to expose pack NTC.
USB-C Footprint / Manufacturer Review
- Auto-route precheck continues to flag same-net overlapping pins inside J1 USB-C VBUS/GND footprint pairs.
- The router treats those overlapping same-net pads as single pins, but the footprint must be reviewed with the intended flex/rigid-flex fabricator before release.
- Confirm pad geometry, solder-mask web, paste apertures, shield/mechanical pads, and whether same-net merged pads are acceptable in the manufacturer DFM flow.
AD5940 Fine-Pitch / Flex Routing Review
- AD5940 remaining airwires are concentrated at fine-pitch ground/reference/signal escape pins.
- Targeted single-connection routing failed on selected AD5940 connections due local congestion; additional auto-route pass did not materially improve results.
- Recommended next action is placement/rule/layout intervention rather than more auto-route retries:
- Move AD5940 support capacitors and electrochemical switch/resistor cluster to improve pin escape.
- Add/confirm manufacturer-specific fine-pitch rules for WLCSP escape routing.
- Consider buried/blind microvias or a 6-layer rigid-flex island if the chosen fabricator supports it.
- Create explicit ground/power plane layer assignments and local stitching strategy.
Routing / Verification Results
- Auto-route first pass routed most of the board but timed out with 26 airwires.
- The resume operation was unavailable; cleanup auto-route pass added 17 routing nodes but finished partial.
- Final DRC snapshot:
- 26 remaining airwires.
- 0 dangling traces after cleanup.
- No overlapping-copper, overlapping-trace, component-overlap, invalid-layer, or outside-board errors returned in the final filtered DRC set.
- Final checked ERC categories reported no ERROR/WARNING results for floating pins, power pins, single-pin nets, undriven nets, or driver conflicts.
Residual Airwire Classes
- AD5940 / electrochemical AFE:
AFE1, GPIO0, VREF_2V5, AD5940 ground/reference pins and fine-pitch escape.
- ADS1292R / ECG AFE: EP/VREFN/GND-related remaining connections.
- Ground stitching / fills: several remaining GND fill/stitch connections.
- USB-C footprint: same-net GND pad pairs still reported as airwire-style pad-to-pad issues.
- SPI/sensor bus: MISO/DOUT/D1 and two trace-end residuals that need targeted review.
Release Status
This revision is not ready for manufacturing. It is a routed concept with a finalized first-pass safety interlock and charger settings, but residual airwires and manufacturer-dependent fine-pitch/flex constraints remain open.
2026-07-27 Follow-up: AD5940 Re-placement + 6-Layer Routing Attempt
- Removed the previous partial PCB routing before reroute to avoid preserving congestion around the AD5940 island.
- Changed the PCB routing assumption from 4 copper layers to 6 copper layers while preserving the custom flexible patch outline.
- Re-placed the AD5940 electrochemical island:
- U7 remained central in the electrochemical island.
- C15/C16/C17/C18/C19 were moved to the bottom side around U7 to shorten reference/supply loops while opening top-side BGA escape.
- R19-R24 and U12/U13 were pushed outward toward J4 to preserve the intended J4 → resistor/switch → AD5940 signal flow.
- Added advanced-fab routing baseline rules:
- 75 µm trace / 75 µm clearance preference for dense fine-pitch escape.
- 0.45 mm pad / 0.20 mm drill via baseline for dense routing.
- These are not manufacturer-approved constraints; they require confirmation with the selected rigid-flex fabricator.
- Rerouted from a clean copper state. Result improved the original AD5940 congestion but final manufacturing gate still failed.
Final Gate After Follow-up
- Manufacturing export was intentionally not run because the board still has 24 airwires.
- Dangling traces: 0 after cleanup.
- Blocking copper overlap, invalid-layer, body-overlap, and outside-board errors were not present in the final filtered DRC snapshot.
- Checked ERC categories again reported no ERROR/WARNING results for floating pins, power pins, single-pin nets, undriven nets, or driver conflicts.
Remaining Airwire Classes After Follow-up
- AD5940 fine-pitch escape: AFE1, GPIO0, VREF_2V5, DGND/AGND/AGND_REF, and related local reference/ground connections.
- ADS1292R / ECG control and SPI links: DRDY, PWDN/RESET, MISO/MOSI-related endpoints.
- GND stitch/fill to AD5940 and switch/AFE local grounds.
- SWDCLK/SWDIO route fragments introduced by cleanup of overlapping router geometry.
- A few router trace-end artifacts remain reported as airwire endpoints, but no dangling traces remain.
Updated Recommendation
Do not export or manufacture this revision. The next realistic path is manual AD5940/ADS1292 fanout planning with a fabricator-approved 6-layer rigid-flex/microvia stackup. If the target manufacturer cannot support 75 µm trace/space and appropriate laser microvias/via-in-pad around the AD5940, split the AD5940 onto a rigid island or replace the package/architecture.