Wearable Health Patch

Prepared the PCBWay DFM submission materials and regenerated the STEP model. I can’t submit to PCBWay directly from Flux, but these files are ready for you to upload to PCBWay’s rigid-flex/HDI quote channel for engineering feedback.
Project files:
Upload package:
Open items:
  • Final assembly is still incomplete: DRC has unresolved airwires.
  • Use these files for PCBWay engineering review only, not fabrication release.
  • After PCBWay provides the approved stackup/via table, manually finish AD5940/ADS1292 fanout, clear airwires, rerun DRC, then regenerate final exports.
I’ll inspect the current PCB state, determine whether placement, routing, or both need work, then run the appropriate auto-layout operations and verify the applied result.
Blocked: your account currently has no available ACUs, so AI inspection and auto-layout operations are unavailable.
Current known project state:
  • 6-layer rigid-flex working layout.
  • AD5940 support placement previously reorganized.
  • PCBWay HDI-oriented rules applied.
  • Last verified state had 24 unresolved airwires.
No PCB changes were made in this session. Remaining work is to inspect the latest board state, determine whether placement and/or routing is needed, run auto-layout, apply the result, and verify DRC once ACUs are available.
Check ACU balance
List airwires
Check DRC/ERC
Manual placement review

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Manual Routing Fix Report — PCBWay HDI Rigid-Flex Export
Status
Exported for review/manual repair only — not ready for fabrication release.
Date: 2026-07-27
Project: Neura Vital Patch
Target manufacturer assumption: PCBWay 6-layer rigid-flex HDI
Target Manufacturer / Stackup Decision
Selected working fabrication target: PCBWay rigid-flex / HDI quotation path.
Reason:
  • PCBWay advertises 6-layer rigid-flex PCB options.
  • Search-visible PCBWay capability references include up to 16-layer rigid-flex, 2/2 mil headline trace/space, 4 mil minimum via, and examples with laser holes around 0.10 mm on advanced rigid-flex builds.
  • This is the best cost/availability fit for prototype iteration, but it is not yet an approved stackup.
Locked Working Rules in Layout
The layout now contains PCBWay-oriented working rules:
  • 6 copper layer routing assumption.
  • 75 µm trace/space baseline for dense HDI/fine-pitch escape.
  • 0.25 mm pad / 0.10 mm laser-microvia review target for dense AD5940 escape.
  • 0.45 mm pad / 0.20 mm drilled via baseline remains in the layout for conventional dense routing.
  • USB 2.0 differential pair still requires final impedance calculation after PCBWay confirms dielectric stack.
Important Caveat
Flux currently still represents the stackup/vias generically. The exported files do not prove PCBWay will accept the microvia/via-in-pad construction. Send the Gerbers plus this report to PCBWay engineering and request explicit confirmation of:
  • 6-layer rigid-flex stackup.
  • Which zones are rigid versus flex.
  • 75 µm trace/space availability on the rigid AD5940 island.
  • Laser microvia diameter/capture pad and whether via-in-pad is allowed/filled/capped.
  • Whether stacked or staggered microvias are allowed.
  • USB-C footprint pad geometry and same-net merged VBUS/GND pads.
  • Bottom-side 0402 passives near the AD5940 island.
  • Minimum bend radius and no-component/no-via bend-zone rules.
Final Verification Snapshot
  • Final DRC: 24 airwires remain.
  • Dangling traces: 0.
  • Blocking overlapping-copper errors in the final filtered check: none reported.
  • Missing footprints / invalid layers in the final filtered check: none reported.
  • Checked ERC categories: no ERROR/WARNING for floating pins, power pins, single-pin nets, undriven nets, or driver conflicts.
Manual Routing Problem List
The following are the remaining unrouted connections reported by Flux after the final route pass. These are the points to fix manually.

Table


#Reported endpoint / net clueLikely functional areaRecommended manual action
1SWDCLK/TCKSWD debugRe-route J5 SWDCLK to U1 with a clean signal path; avoid crossing antenna keepout.
2AFE1 / GLU_CEAD5940 electrochemical CE pathManually fan out U7 AFE1 ball; consider via-in-pad or local microvia to inner signal layer before leaving U7.
338ff48a5 through-hole pairRouter via/stitch artifactInspect associated via/pad pair; reconnect or delete/recreate as a valid via transition.
4GPIO0 / ECHEM_INTAD5940 interrupt to nRF52840Escape U7 GPIO0 with microvia/inner-layer route, then route to U1 P0.24.
5ADS1292R ~DRDYECG AFE data-readyManually route U5 DRDY to MCU; preserve spacing from ECG analog inputs.
6Trace e252 / via endpointRouter via artifactInspect and reconnect/remove associated trace/via stub.
7ADS1292R ~PWDN/~RESETECG AFE reset/powerdownManually route U5 reset/powerdown to MCU/control net.
8D1 U12→U7Electrochemical switch outputRoute U12 D1 to U7 SE0/related electrode path with short, quiet analog routing.
9AD5940 DGND internal pinsAD5940 ground fanoutAdd local ground microvias/via-in-pad from U7 DGND balls to ground plane; confirm fabrication support.
10AD5940 DGND internal pinsAD5940 ground fanoutSame as above; avoid daisy-chaining ground balls with long surface traces.
11AD5940 AGNDAD5940 analog groundTie to local analog/solid ground plane with short via; review AGND/DGND strategy.
12AD5940 DGND internal pinsAD5940 ground fanoutUse local vias to plane; verify no isolated ground islands.
13AD5940 AGND_REFAD5940 reference groundRoute/plane-tie reference ground carefully; keep away from switch node/noisy digital.
14C16 P2 / GND to U7 DGNDAD5940 VREF_2V5 cap returnPlace/route C16 ground return directly to U7 reference/ground via; bottom-side capacitor likely needs local microvia.
15GND stitch to U9 SDO/ADDRAccelerometer address tieResolve local ground tie/stitch near U9.
16GND stitch to U9 GNDAccelerometer groundAdd/adjust ground stitch via or direct ground pour connection.
17GND stitch to U11/U12 switch groundPatient switch groundAdd local switch ground stitch/route; ensure patient switch control return is quiet.
18U5 VREFN / cap ground clueADS1292R reference returnManually route ADS1292R reference ground/cap return with short loop.
19U1 P0.15 / ADS1292R DOUTSPI MISO / ECG DOUTRoute SPI MISO cleanly from U5/U7 to U1; avoid analog front-end inputs.
20U13 D1 / U7 AIN1Glucose WE pathRoute electrochemical switch output to AD5940 AIN1; keep high impedance/low leakage.
21Trace c879 / patient switch controlPatient switch control route artifactInspect and reconnect/delete partial PATIENT_SW_CTRL trace endpoint.
22U1 P0.14 / U7 MOSISPI MOSIRoute MCU MOSI to U7/U5; use inner signal layer if top-side congestion remains.
23Trace 82d4 / U7 CSAD5940 chip selectInspect partial CS_ECHEM_N trace endpoint; reconnect to U7 CS.
24U7 VREF_2V5 / C16 P1AD5940 reference capacitorCritical: route C16 directly to U7 VREF_2V5 with shortest path; likely needs microvia/via-in-pad or cap reposition.
Manual Fanout Recommendation
For the AD5940 0.4 mm-pitch BGA/WLCSP area:
  1. Treat U7 as a rigid-island HDI component, not generic flex routing.
  2. Place local ground/reference microvias at AD5940 ground/reference balls if PCBWay approves via-in-pad or dogbone microvia fanout.
  3. Keep C15-C19 bottom-side only if the mechanical stack allows bottom-side parts under/near the patch.
  4. Route critical reference/ground caps first: C16 VREF_2V5, C15 VREF_1V82, C17 VBIAS_CAP, C18 AVDD_REG, C19 DVDD_REG.
  5. Route electrochemical analog paths next: AFE1, AIN1, AIN2, SE0, CE0, RE0.
  6. Route SPI/control last, keeping it away from ECG/electrochemical high-impedance nodes.
Export Package Warning
The generated Gerber/BOM/PnP/netlist/STEP files are useful for visual review and PCBWay engineering feedback, but they should not be ordered for assembly until all 24 airwires are resolved and the manufacturer approves the HDI rigid-flex construction.
2026-07-27 Submission Package Update
  • Regenerated Gerber ZIP for PCBWay DFM review.
  • Regenerated STEP model for mechanical/assembly review, even though the final assembly/routing is incomplete.
  • Created a separate PCBWay DFM review request markdown file to upload alongside the Gerbers.
  • Created PCBWay DFM Submission Instructions in the project files.
  • Current instruction: submit the package only for engineering feedback; do not place a fabrication/assembly order until PCBWay approves the stackup/rules and all airwires are manually cleared.
  • Status

  • Target Manufacturer / Stackup Decision

  • Locked Working Rules in Layout

  • Important Caveat

  • Final Verification Snapshot

  • Manual Routing Problem List

  • Manual Fanout Recommendation

  • Export Package Warning

  • 2026-07-27 Submission Package Update

Neura Vital Patch thumbnail
Schematics and PCB layout for Neura Vital Patch with parameters

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