Wearable Health Patch
Worked for 30 sec
Prepared the PCBWay DFM submission materials and regenerated the STEP model. I can’t submit to PCBWay directly from Flux, but these files are ready for you to upload to PCBWay’s rigid-flex/HDI quote channel for engineering feedback.
Project files:
Upload package:
Open items:
- Final assembly is still incomplete: DRC has unresolved airwires.
- Use these files for PCBWay engineering review only, not fabrication release.
- After PCBWay provides the approved stackup/via table, manually finish AD5940/ADS1292 fanout, clear airwires, rerun DRC, then regenerate final exports.
Start Auto-Layout
Thought for 13 sec
I’ll inspect the current PCB state, determine whether placement, routing, or both need work, then run the appropriate auto-layout operations and verify the applied result.
Thought for 22 sec
Blocked: your account currently has no available ACUs, so AI inspection and auto-layout operations are unavailable.
Current known project state:
- 6-layer rigid-flex working layout.
- AD5940 support placement previously reorganized.
- PCBWay HDI-oriented rules applied.
- Last verified state had 24 unresolved airwires.
No PCB changes were made in this session. Remaining work is to inspect the latest board state, determine whether placement and/or routing is needed, run auto-layout, apply the result, and verify DRC once ACUs are available.
Check ACU balance
List airwires
Check DRC/ERC
Manual placement review
Refine this doc
Ask about this doc
Board Bring-Up Plan — Neura Vital Patch
Prerequisites
- Current-limited bench supply or USB current meter.
- DMM and oscilloscope.
- SWD programmer compatible with nRF52840.
- ECG simulator, electrochemical dummy cell, pressure source, and optical/contact fixture for later functional validation.
- Safety: do not connect to a human subject during first bring-up.
1. Visual Inspection
- Verify polarity/orientation of U2 charger, U3 buck-boost, U4 LDO, U5/U7 AFEs, U6 optical sensor, USB-C, and JST battery connector.
- Inspect AD5940 WLCSP/BGA soldering carefully.
- Confirm no components/vias are in flex bend zones after layout is finalized.
2. Power Rail Verification
Table
| Rail | Source | Expected | Measure At | Initial Current Limit | Pass Criteria |
|---|---|---|---|---|---|
| USB_VBUS | USB-C J1 | 5 V nominal | J1/U2 IN | 100 mA first power | No short, no hot parts |
| BAT_PLUS | J2 LiPo | 3.0–4.2 V | J2/U2 BAT | 100 mA first power | Correct polarity and no short |
| SYS_RAW | U2 OUT | battery/SYS level | U2 OUT/U3 VIN | 100 mA first power | Stable source to buck-boost |
| VSYS_3V3 | U3 TPS63031 | 3.3 V | U3 VOUT/C3/C4 | 150 mA then increase | 3.3 V ±5%, acceptable ripple |
| VDD_1V8 | U4 LDK130 | 1.8 V | U4 OUT/C6/C13 | 50 mA | 1.8 V ±5% |
Procedure:
- Check resistance from USB_VBUS, BAT_PLUS, SYS_RAW, VSYS_3V3, and VDD_1V8 to GND before power.
- Power from current-limited USB or bench 5 V at J1.
- Confirm U2 OUT, U3 3.3 V, and U4 1.8 V before connecting battery.
- Confirm charger status with a protected LiPo pack and thermal monitoring.
3. Critical Signals
Table
| Signal | Expected State | Notes |
|---|---|---|
| MCU_RESET_N | High after power-up | SW1 pulls low |
| SWDIO/SWDCLK | Programmer activity | J5 |
| I2C_SCL/SDA | 3.3 V pull-up idle | R9/R10 |
| CS_ECG_N / CS_ECHEM_N / ACCEL_CS_N | High idle | Pull-ups R11–R13 |
| PATIENT_SW_CTRL | Low/disabled at boot | Must remain disabled while USB attached |
| CHG_PGOOD_N / CHG_STAT_N | Depends on USB/charge state | Read via MCU |
4. Connector and Interface Tests
Table
| Connector | Pins | Test |
|---|---|---|
| J1 USB-C | VBUS, GND, CC1/CC2, D+/D− | Check 5.1 kΩ CC pull-downs and USB continuity |
| J2 Battery | BAT_PLUS/GND | Polarity, charge behavior with protected pack |
| J3 ECG FPC | ECG_RA_RAW, ECG_LA_RAW, ECG_RLD_RAW | Continuity through resistors/switches to ADS1292R |
| J4 Electrochemical FPC | LAC/GLU WE/RE/CE | Continuity through protection/switches to AD5940 |
| J5 SWD | VTref, GND, SWDIO, SWDCLK, RESET | Programmer detects nRF52840 |
5. Programming and Debug
- Connect SWD to J5.
- Confirm target voltage on VTref = 3.3 V.
- Read nRF52840 device ID.
- Flash firmware starter.
- Confirm serial/debug output and BLE advertising.
6. Functional Validation
Table
| Test | Components | Expected Result |
|---|---|---|
| I2C scan | U6/U8/U9/U10 | Devices respond at expected addresses |
| SPI register read | U5/U7 | Device ID/status registers readable |
| ECG simulator | J3/U5 | Stable ECG waveform, lead/contact detection |
| Electrochemical dummy cell | J4/U7 | Current/impedance response matches dummy cell |
| PPG fixture | U6 | Valid FIFO/interrupt behavior |
| Pressure fixture | U8 | Pressure transfer function matches applied pressure |
| Motion | U9 | Acceleration responds to orientation/motion |
| Fuel gauge | U10 | Battery voltage/SOC reasonable |
| Safety lockout | U11–U13 + USB | Patient switches disabled when USB present |
7. Open Bring-Up Risks
- BQ24074 programming values and TS network are provisional.
- TPS63031 final power-stage values require datasheet/layout review.
- Patient leakage must be measured before any human-use testing.
- Electrochemical and ECG front-end support values need reference-design refinement.
8. 2026-07-27 Safety/Routing Update
- Added hardware USB-forced patient disconnect interlock: USB_VBUS now drives Q1/R27/R28 to clamp PATIENT_SW_CTRL low; R25 limits MCU contention and R26 defaults switches off.
- Added RT1 10 kΩ NTC on BQ24074 TS and removed the fixed TS placeholder; verify RT1 is thermally bonded to the LiPo cell during assembly.
- Charger ISET finalized to 8.87 kΩ for ~100 mA fast charge; ILIM resistor set to 8.06 kΩ for ~200 mA if resistor-programmed input-limit mode is used.
- Final routing verification still has 26 airwires, so do not use this board for manufacturing or bring-up until routing is completed and DRC is clean.
- Bring-up must include a USB-attached safety test proving PATIENT_SW_CTRL is low and electrode paths are open before any electrode fixture or human-use testing.
9. 2026-07-27 Manufacturing Gate Update
- Manufacturing export was blocked because final routing DRC still reports 24 airwires.
- Do not assemble or bring up this PCB revision until routing is completed and the manufacturer-approved rigid-flex stackup is locked.
- Bottom-side AD5940 support capacitors were introduced; bring-up/mechanical planning must verify bottom-side component clearance, encapsulation, and no placement in active bend regions.
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signals
4. Connector and Interface Tests
5. Programming and Debug
6. Functional Validation
7. Open Bring-Up Risks
8. 2026-07-27 Safety/Routing Update
9. 2026-07-27 Manufacturing Gate Update
