The controller uses three independently supervised processors. MCU1/U90 remains ESP32-WROOM-32 for ATTESA/A-LSD and directly captures five high-speed PCNT sources: four shared conditioned wheel speeds (GPIO17/16/19/18) plus isolated RPM TACH_INPUT (GPIO26). MCU1 GPIO4 commands the A-LSD PWM solenoid through U7 gate 3 and U4 channel 0 to J_OUT cavity 11. MCU1 GPIO27 commands the ATTESA pump relay through U7 gate 4 and U5 channel 1 to J_OUT cavity 12; the required relay-drive current is 1 A maximum.

MCU3 directly captures ST-A/ST-B/ST-Z on GPIO4/5/6 with GPIO7 reserved as a fourth PCNT-capable spare. It directly receives protected brake GPIO8, TPS GPIO10/ADC1 and reverse GPIO11. GPIO9 is reserved for handbrake but remains no-connect because the live design has no connector or electrically complete protected handbrake front end. MCU1 no longer directly receives brake or TPS; MCU2 no longer receives reverse. Brake is intentionally hardwired to both MCU2 and MCU3: MCU2 requires a local brake state so ABS remains autonomous if MCU3 or I2C fails, while MCU3 owns distribution and low-speed plausibility.

R34_GTR_Steering_Angle_Sensor_Pinouts.txt is authoritative: ST-A TCU pin24 and ST-B pin27 are 0–5 V quadrature square waves; ST-Z TCU pin28 is a 0–5 V center-index pulse, one pulse/revolution; signal ground returns to TCU pin30. Sensor power is switched +12 V from the ignition relay. J_STEER maps pins 1/2/3/4 to TCU 24/27/28/30. Each signal uses a 12 kΩ upper plus 22 kΩ lower divider (5 V nominal becomes 3.24 V) and a 3.3 V-referenced SRDA3.3 clamp before the MCU3 PCNT GPIO. No bandwidth-limiting capacitor or assumed pull-up was added because output impedance and maximum frequency are not supplied.

Open steering blockers: counts per revolution, A/B phase convention, pulse widths/maximum frequency, output-drive topology/source impedance, tolerances beyond nominal 0–5 V, and center/index mechanical calibration are absent. These require bench/scope characterization before safety validation; firmware must mark steering invalid until characterized limits and plausibility tests pass.

All three MCUs share one 3.3 V I2C bus with exactly one pull-up pair, R16/R200 = 3.3 kΩ. Normal coordinator is MCU1. Unique logical endpoints are MCU1 0x30, MCU2 0x31, MCU3 0x32. Packet ownership, fixed headers, little-endian sequence/timestamp/validity fields, CRC-16/CCITT-FALSE, local receive-age rules and recovery criteria are specified in firmware-starter.

Existing MCU2-to-MCU1 heartbeat remains GPIO48→GPIO35. MCU3 adds dedicated heartbeat/fault outputs GPIO12→MCU1 GPIO25 and GPIO13→MCU2 GPIO10. Nominal edge period is 20 ms and timeout is 100 ms. Invalid/stale MCU3 data causes MCU1 torque disengagement and removes authorization. MCU2 continues only autonomous ABS functions supported by local wheel and duplicated brake inputs; strategies requiring steering/TPS/reverse/handbrake are inhibited and warnings/fault state asserted. Recovery requires ten consecutive valid sequence-progressing packets, heartbeat health and local plausibility.

Critical S3 functions avoid GPIO0/3/45/46 straps, GPIO19/20 native USB, GPIO43/44 UART0, and GPIO35/36/37 memory-risk pins on MCU3. MCU2 is the verified N8/no-PSRAM module; its existing GPIO35/36/37 diagnostic selects remain allowed for that exact variant. Preserve antenna keepout regions for all ESP32 modules and keep the MCU3 DevKit USB connector mechanically accessible.

U80 brownout supervision, U81 watchdog, command pull-downs and 74HC08 authorization remain authoritative. The A-LSD and pump-relay gated commands each have a 10 kΩ default-off pull-down and require ACTUATOR_ENABLE. Reset, brownout, watchdog failure, controller-disable, stale heartbeat, invalid packet or task-health failure forces local command outputs LOW and withdraws authorization.

The shared PCB power path feeding the ABS output drivers shall be rated and qualified for 30 A continuous and shall survive a 60 A fuse-clearing transient, with transient duration and I²t defined by the external vehicle-side fuse time-current curve. The fuse is external to the controller; no additional internal or PCB-mounted fuse is required. Control strategy shall prevent more than four ABS solenoids from being energized simultaneously and shall keep their combined surge current at or below 30 A.

Each individual ABS solenoid output, ATTESA main/failsafe solenoid output, and A-LSD solenoid output shall be rated for 10 A, including driver channel, PCB branch copper, connector contact, terminal and harness conductor. The 10 A individual rating does not permit simultaneous activation that violates the shared 30 A ABS-path limit.

The ATTESA pump-relay output remains a relay-coil-only circuit with a 1 A maximum required output rating and approximately 0.2 A expected load. Do not upgrade this output or use it for direct pump-motor drive/PWM.

These are design requirements rather than claims of current hardware compliance. Production release requires verification of the connector/contact group, fuse and holder, shunt, disconnect MOSFET stage, PCB copper/neckdowns, all layer transitions, solder joints and thermal environment at 30 A steady state and against the final fuse's 60 A clearing pulse/I²t.

The J1-J5 to J_MAIN migration was re-evaluated against all retained pinout attachments and the Nissan/TE evidence on 2026-08-12. Do not remove or rewire J1-J5 and do not create a guessed 76-way footprint. The latest AI-authored TXT revisions are not a cavity authority: the service-derived variants conflict on power, wheel, ABS-valve, steering and ATTESA/A-LSD terminals. In particular, one claimed scheme uses small cavities 1-57 and large cavities 101-120, while the verified TE 76-position header evidence for 7-5174385-5 / 174385 family uses 60 small cavities 1-60 plus 16 large cavities 101-116. Therefore cavity 120 is outside the verified header scheme.

TE confirms 7-5174385-5 as a 76-position, 2-row, horizontal board-mount header with through-hole termination and 2.5/3.8 mm mixed centerlines. TE-derived 174385-family data confirms 60 × 1.0 mm plus 16 × 1.8 mm tabs. However, no authoritative GT-R supplement connector-view table has yet tied the BNR34 ATTESA/ABS terminal numbers to that header's mating-face/PCB-side cavity numbering, and the exact product drawing hole coordinates, keying, pin-1 landmark and mounting features have not been imported/verified in Flux. The exact part is absent from the Flux library.

Migration may resume only after: (1) a legible Nissan BNR34 Service Supplement terminal table and connector-view drawing are transcribed with each used cavity unique and within 1-60/101-116 (or a different OEM header is authoritatively proven); (2) the exact TE customer drawing and a traceable footprint are verified; and (3) low-side stages for OEM2/OEM13/OEM14 and protected monitors for OEM103/OEM108 plus the correct floating/bidirectional ATTESA/A-LSD output topology are present. RPM and external ATTESA pressure remain on dedicated auxiliary connectors unless an OEM cavity is proven. External steering and J_IO remain preserved.

The protected breakout uses TE AMPSEAL 776231-1, 35 cavities. MCU1 GPIO4 and GPIO27 were reclaimed for the two new actuator commands, so cavities 1 and 3 are now NC/reserved and their series/ESD exposure parts were removed. Cavities 1–3, 30–35, and any other listed reserved positions require cavity plugs.

Automotive I/O protection: the six non-automotive PRTR5V0U4D,125 arrays were removed. Each of the 23 general spare-I/O cavities is protected to GND by its own TI ESD601DPYRQ1 (ESD601-Q1) bidirectional diode while retaining the existing 1 kΩ series resistor. Datasheet evidence: AEC-Q101 HBM/CDM test references; ±15 kV IEC 61000-4-2 contact/air and ISO 10605 ratings; 18 V reverse working standoff; 0.3 pF typical / 0.5 pF maximum line capacitance; 1 nA typical / 10 nA maximum leakage at 18 V. The 18 V standoff is well above normal 3.3 V signaling, so it does not clip valid GPIO/ADC levels, and its very low capacitance/leakage preserves PCNT edges and low-speed ADC usability. The existing cavity-25 handbrake protection also uses this automotive -Q1 device.

Draft architecture only; not ISO 26262 certified. Vehicle use requires HARA, FMEA/FMEdA, FTTI, EMC/transient, thermal/derating, hydraulic-safe-state and software verification.

The release architecture uses one TE DEUTSCH DRC13-40PC 40-way right-angle main connector on the bottom edge and one TE 6473423-1 26-way right-angle spare connector on the left edge. The spare connector is implemented as J_SPARE: 21 protected spare I/O channels, two GND returns, 3V3 and 5V low-current references, and one NC cavity. LED_CASE_ABS remains at the top edge opposite the main connector.

Permanent battery must not boot the system. Two permanent +12 V contacts feed VBAT_RAW ahead of the existing fuse/reverse/load-dump stage. Switched +12 V is a low-current sense input only and drives LM74930-Q1 EN through AEC-Q101 BAS116-QR reverse/backfeed isolation, three 100 kΩ series resistors, a 100 kΩ default-OFF pull-down and 470 nF deglitch capacitor. Ignition absent therefore leaves the protected rail, regulators and controllers off except LM74930 shutdown current (2.5 µA typical, 5 µA maximum) and unavoidable front-end leakage. Watchdog, brownout and actuator authorization remain downstream and unchanged.

Final main-connector migration is blocked: Flux has no exact DRC13-40PC and the official drawing's graphical PCB hole coordinates/cavity orientation could not be extracted authoritatively. No footprint was guessed. J_IO and J_POWER therefore remain temporarily; their final removal is a release gate. The target 40-cavity map and interim allocation are maintained in connector-and-harness-map.