Raspberry Pi Carrier Board Design

Worked for 12 sec

flux

Updated routing/placement plan before proceeding:

Do not route yet. First close/accept layout-footprint status:
- Ag59624-LPB footprint: validated structurally.
- KMB210S footprint: pin mapping confirmed correct: 1=AC, 2=AC, 3=+, 4=-.
- EEH-ZK1H471P footprint: conditionally valid pending size-code G confirmation.
- TCST2103 footprint: pending pin-function confirmation before replacement.
Layout setup
- Use 4-layer stackup minimum.
- Layer intent: Top signals/components, Inner1 solid GND reference, Inner2 power distribution, Bottom secondary signals.
- Controlled impedance required for Ethernet: 100Ω differential.
- USB 2.0 D+/D- should be treated as 90Ω differential if routed as high-speed.
Placement order
- Place fixed/mechanical connectors first: vertical RJ45, CM connector, CSI, USB, LiDAR JST-GH, motor JST-XH, tamper/debug/service headers.
- Place PoE/isolation block next with 6.4mm isolation barrier preserved.
- Place power converters and bulk caps near their loads.
- Place CM support/debug/camera circuits.
- Place TPM/RTC in digital low-noise area; no TPM SPI test pads.
- Place TMC2209 X/Y drivers near motor connectors but away from CSI/Ethernet/TPM/RTC.
- Place PAN/TILT optical home sensors according to mechanical homing geometry.
Routing order
- Power/grounds and star-point strategy first: GND_MOTOR / GND_DIGITAL star near buck input bulk; GND_PE_ISOLATED isolated except Y-cap.
- Ethernet differential pairs next with 100Ω diff, continuous reference plane, pair matching.
- USB 2.0 pair next.
- CSI camera differential lanes next, length-aware and referenced to solid GND.
- SPI TPM, I2C RTC/camera, UARTs, homing/tamper/debug GPIOs.
- Motor outputs and +24V/+12V/+5V power traces last with adequate width/clearance, kept away from sensitive nets.
Validation gates
- After placement: run DRC/review and get your approval before routing.
- Before routing: pre-route board check.
- After routing: DRC/ERC, airwire check, impedance/clearance review, BOM/netlist regeneration.

I will not start placement or routing until you explicitly approve the next phase.

Approve placement phase

Close footprint blockers

Confirm capacitor package

Finish TCST mapping

Set layout constraints

Files

Schematic

Layout

3D View

Power Architecture Budget

Scope

Block 2 pre-schematic power architecture for the PoE++ PD subsystem, isolated 24V rail, 5V buck rail, and local 3.3V buck rail. No schematic nets have been drawn yet.

Confirmed Decisions

Input power is IEEE 802.3bt PoE++ Type 3, 60W class.
PoE module is Silvertel Ag59624-LPB: isolated 24V output, 51W continuous, 60W peak.
The earlier Ag9912 reference is rejected; it is not the correct 24V/45W+ family for this project.
Local 3.3V rail is generated by a TPS62160-based 5V-to-3.3V buck converter, not by the CM internal 3.3V rail and not by a small SOT-23 LDO.
No firmware-side power limiting is required for expected load-envelope compliance because the simultaneous peak estimate is inside the PoE++ Type 3 usable budget.

Selected PoE++ PD Module

Table

Requirement	Selected Part: Silvertel Ag59624-LPB	Result
IEEE 802.3bt Type 3 compliant minimum	Type 3, Class 6 IEEE 802.3bt PD	Pass
24V isolated output	24V nominal single output	Pass
Usable power at PD	51W continuous, 60W peak	Pass
Industrial temperature	-40°C to +85°C ambient	Pass
Active distribution	DigiKey lists AG59624-LPB; Mouser lists Ag59624-LPB and tape/reel variants	Pass
Isolation	1500V input-to-output isolation barrier	Pass
Efficiency	About 93% peak per Silvertel data	Pass

Power Tree

Diagram

Rail Load Budget

Table

Rail	Load	Typical Current	Peak / Design Current	Power at Rail	Notes
5V	CM4/CM5 module plus USB boot support	1.5A	3.0A	7.5W typical, 15W peak	TPS54331 target output is 5V/3A to meet CM carrier guidance.
5V	TPS62160 3.3V buck input	0.14A	0.24A	0.62W typical, 1.06W peak at 3.3V output	Assumes 90% efficiency for 3.3V at 0.17A typical / 0.32A peak after removing the previously planned location module load.
3.3V	TPM, RTC, TMC2209 logic, pull-ups, small status/debug loads	0.17A	0.32A	0.56W typical, 1.06W peak	TPS62160 gives 1A capacity with large margin.
+24V_MOTOR	Three TMC2209 motor VM/VS rails	0.375A	0.625A	9W typical, 15W peak	Estimate for three NEMA 11 motors at 0.67A/phase with chopper drive. VM/VS here refers to TMC2209 pins.
+24V_MOTOR	TPS54331 input for 5V rail	0.40A	0.79A	9.6W typical, 19.1W peak	Assumes 85% efficiency: Pin = 5V * Iout / 0.85. Includes CM and 3.3V buck input power.
+24V_MOTOR	TVS leakage, housekeeping margin	0.02A	0.05A	0.5W typical, 1.2W peak	Design margin placeholder.
+24V_MOTOR	Total +24V_MOTOR output demand	0.80A	1.46A	19.1W typical, 35.3W peak	Fits inside 51W continuous PoE++ Type 3 PD budget.

PoE++ Headroom Check

Table

Source / Conversion Stage	Available or Required Power	Result
IEEE 802.3bt Type 3 PSE source class	60W class	Standard PoE++ Type 3 source class.
PD usable budget with selected Ag59624-LPB	51W continuous, 60W peak	Meets project requirement of at least 45W usable.
Estimated typical demand	19.1W	Fits with about 32W headroom.
Estimated simultaneous peak demand	35.3W	Fits with about 15.7W headroom.
+24V_MOTOR rail current at 51W	2.125A continuous	Above estimated 1.46A peak demand.
Conclusion	System remains inside the standard power envelope under all expected load conditions	No firmware-side power management required for power-budget compliance. Motion current limits are still needed for motor/driver thermal control.

Selected Power Components for Schematic Planning

Table

Function	Selected / Target Component	Key Rating	Distributor / Datasheet Status	Decision
PoE++ PD isolated +24V_MOTOR output	Silvertel Ag59624-LPB	IEEE 802.3bt Type 3 Class 6, 24V, 51W continuous, 60W peak, -40°C to +85°C	DigiKey/Mouser distribution observed previously	Approved baseline.
PoE input bridge rectifiers	2x SMC Diode Solutions KMB210S	Schottky bridge, 100V VRRM, 2A average rectified current, MBS SMD package	DigiKey 1655-1889-1-ND / KMB210STR observed; 24k+ stock reported by DigiKey scrape. Mouser datasheet family found for MB22S-MB210S.	Use two bridges, one per PoE pair-set, for polarity handling with low Schottky loss. This replaces HD06-T/MB6S suggestions because HD06-T is not a 1.5A Schottky bridge and MB6S-class parts are commonly below the requested current.
PoE output bulk capacitor	Panasonic EEH-ZA1H471P	470uF, 50V, conductive polymer hybrid aluminum, ZA series, AEC-Q200, -55°C to +105°C minimum	Corrected real Panasonic MPN. The previously listed EEH-ZA1H102P is invalid because the ZA series 50V family does not include a 1000uF variant.	Locked preferred part for the +24V_MOTOR rail bulk capacitor. Required capacitance estimate: I/(fdV) = 1.5A/(100kHz0.1V) = 150uF; 470uF gives about 3x margin. Standard wet-electrolytic capacitors are rejected for the industrial-life requirement.
PoE input surge protection	SMJ58A or equivalent per Ag59600/Ag59624 typical diagram	Protects against input over-voltage surges	Final TVS selection during protection block	Candidate only.
Isolation Y-capacitor	Murata DE2E3KY102MA2BM01	1000pF, Y2 safety class, 250VAC, 1.5kV impulse, radial	DigiKey page found: DE2E3KY102MA2BM01 / 1021465. Mouser page found for DE2E3KY102MA2BM01F.	Locked safety capacitor across GND_PE_ISOLATED to GND_DIGITAL.
+24V_MOTOR TVS	SMAJ40CA class or equivalent for motor outputs; final rail-level TVS class per Block 6	Working standoff above normal 24V and suitable surge rating	Part class defined; exact rail-level part may be selected during schematic capture	Place after isolated PD output, referenced to post-isolation ground strategy.
5V buck	TPS54331	3.5V to 28V input, 3A output	TI datasheet required during schematic block	Approved for 24V to 5V/3A subject to thermal layout and datasheet component values.
3.3V buck	TPS62160	3V to 17V input, 1A output, adjustable 0.9V to 6V, 3mm x 3mm WSON/QFN family	TI datasheet required during schematic block	Replaces AP2112K LDO. Provides high efficiency and low thermal rise in IP54 enclosure.

TPS62160 3.3V Buck External Components

Table

Reference Function	Value / Part Guidance	Datasheet Basis
IC	TPS62160 adjustable buck converter	3V to 17V input, 1A output.
Inductor	2.2uH, saturation current at least 1.4A, low DCR; TDK VLF3012ST-2R2M1R4 class acceptable	Datasheet component list uses 2.2uH, 1.4A.
Input capacitor	10uF, 25V, X7R or X5R ceramic, placed close from VIN to PGND	Datasheet recommends 10uF for most applications.
Output capacitor	22uF, 6.3V or higher, X7R or X5R ceramic, placed close to inductor/output return	Datasheet recommended output capacitor is 22uF.
Feedback divider	R1/R2 = (VOUT / 0.8V) - 1 = 3.125 for 3.3V output	Choose R2 = 100kΩ, R1 = 316kΩ 1% as starting values.
PG pull-up	100kΩ to 3.3V if power-good is monitored	Datasheet example shows 100kΩ.
Thermal note	At 3.3V, 0.35A peak, Pout = 1.155W. At 90% efficiency, loss is about 0.13W.	Runs cool compared with the rejected LDO loss of about 0.6W, even in a sealed enclosure at +60°C ambient.

Ground Domains and Isolation

Table

Ground Domain	Connected Circuits	Connection Rule
GND_PE_ISOLATED	PoE input side, magjack chassis, pre-isolation bridge/surge network, pre-isolation side of Ag59624-LPB	Stays galvanically isolated from board ground. No direct copper tie to GND_DIGITAL or GND_MOTOR.
GND_MOTOR	+24V_MOTOR output rail, TMC2209 power side, motor connectors, +24V_MOTOR bulk capacitors	High-current motor return domain. Connects to GND_DIGITAL at one star point near the +24V_MOTOR bulk capacitor of the 5V buck input.
GND_DIGITAL	CM, TPM, RTC, tamper input, TMC2209 logic side, debug, CSI return, 5V buck output return, 3.3V buck output return	Logic and compute return domain. Connects to GND_MOTOR only at the single star point.

Diagram

Isolation Capacitor and Barrier Note

Locked isolation capacitor: Murata DE2E3KY102MA2BM01, 1nF, Y2 safety class, 250VAC, 1.5kV impulse minimum.
Place the Y2 capacitor directly under or adjacent to the Ag59624-LPB isolation-barrier footprint with minimal loop area.
GND_PE_ISOLATED remains galvanically isolated from GND_DIGITAL/GND_MOTOR except for this Y2 capacitor and any formally approved EMC/safety component.
Board-level creepage and clearance between GND_PE_ISOLATED copper and post-isolation copper is 6.4mm baseline.
Reducing the 6.4mm baseline is not allowed unless a formal safety review explicitly approves the reduction.

Power Architecture Conclusion

The selected Ag59624-LPB +24V_MOTOR PoE++ PD module, dual KMB210S Schottky bridges, Panasonic EEH-ZA1H471P 470uF/50V hybrid polymer output capacitor, Murata Y2 isolation capacitor, TPS54331 5V buck, and TPS62160 3.3V buck resolve the previous power-budget and thermal risks. The 470uF value provides about 3x margin over the 150uF minimum transient estimate for 1.5A events at 100kHz with less than 100mV target ripple. The reduced 3.3V load improves rail margin. The design has sufficient PoE headroom for simultaneous CM peak load, three motor drivers at expected peak, TPM/RTC logic, and local logic rails without requiring firmware-side power throttling for budget compliance.

Scope
Confirmed Decisions
Selected PoE++ PD Module
Power Tree
Rail Load Budget
PoE++ Headroom Check
Selected Power Components for Schematic Planning
TPS62160 3.3V Buck External Components
Ground Domains and Isolation
Isolation Capacitor and Barrier Note
Power Architecture Conclusion