Fixing Airwire Errors

Worked for 11 sec

I’ll manually repair the local 5V_PROT copper at C1:P1, then re-run the airwire DRC to confirm it’s cleared.

Worked for 2 mins 25 sec

The stale marker changed to another local 5V_PROT trace segment (Trace 1322), still tied to C1:P1. I’m cleaning that local segment and re-checking again.

Worked for 1 min 41 sec

flux

After removing the stale local segments, DRC now exposes two short 5V_PROT airwires and the board pre-check says routing is feasible. I’m running a focused routing cleanup pass now.

Worked for 11 mins 16 sec

flux

The C1 airwire is cleared, but the cleanup route introduced overlapping-copper DRC errors. I’m removing the offending cleanup traces/vias so we don’t leave the board with shorts, then I’ll re-check DRC.

Worked for 3 mins 1 sec

flux

The cleanup removed the shorts, but it opened several small local airwires/dangling traces. The board check says routing is feasible, but another route pass may introduce new conflicts; I’m stopping here rather than risking further churn.

Thought for 37 sec

flux

I reworked the local C1:P1 / 5V_PROT routing and re-ran DRC. The original C1:P1 airwire was removed, but the repair route introduced other local routing issues; I removed the shorting overlaps, and the latest DRC now shows 4 airwires and 3 dangling-trace warnings, with no overlapping-copper errors in the checked set.

So the board is still not export-ready. The next safe step is a careful manual PCB edit around the affected traces rather than another blind autoroute pass, because the router is now creating cleanup churn.

Manual routing fix

Inspect affected nets

Revert cleanup route

Create repair plan

Check manufacturability

Files

Schematic

Layout

3D View

LampOS RGBWW Controller — Power Budget and Power-Path Notes

Summary

The board is sized around a protected 5 V input rail with a 3 A design target. The largest load is the pair of SK6812 RGBWW LED rings. The ESP32 and logic rail are secondary but require clean 3.3 V regulation and adequate Wi-Fi transient headroom.

Power Tree

Table

Stage	Rail	Purpose	Notes
Input pads	5 V nominal	External battery pack or adapter input	Large solder pads for heavier wiring.
PPTC fuse	5 V protected path	Short/fault protection	3 A hold target, verify trip/hold derating and resistance.
AO3401A P-FET	5 V protected path	Reverse polarity protection	Low-drop reverse protection preferred over diode.
SMBJ5.0A	5 V to GND	Transient/ESD clamp	Place near input after protection as appropriate for clamp strategy.
Bulk capacitor	5 V to GND	LED surge stabilization	1000 uF preferred, 470 uF minimum.
LED rings	5 V	32x SK6812RGBW-WS	Dominant load. Use pours/plane and distributed local bypassing.
TLV75733PDBVR	3.3 V	ESP32 and 3.3 V logic	Include datasheet input/output capacitors.
74AHCT125	5 V logic supply	LED data level shifting	Inputs driven from ESP32 GPIOs, outputs to LED DIN through 330 ohm resistors.

Load Estimate

Table

Rail	Load	Estimate	Basis / Comment
5 V	32x RGBWW LEDs	2.6 A peak target	User-specified worst-case LED load. Firmware brightness limiting recommended.
5 V	74AHCT125	<10 mA typical	CMOS buffer load is small versus LEDs.
3.3 V	ESP32-WROOM-32-N4	250 mA typical Wi-Fi active, 500-700 mA transient allowance	Use regulator and bulk/decoupling for Wi-Fi bursts.
3.3 V	Pull-ups/control leakage	<5 mA	Boot/reset pullups and logic loads.

Summed Current

Table

Case	5 V LED/logic	3.3 V rail reflected through LDO	Total 5 V input estimate
Active typical	0.5-1.5 A	0.25 A	0.75-1.75 A
Bright LED peak target	2.6 A	0.5 A transient allowance	3.1 A transient
3 A source budget	Firmware-limited	0.3-0.5 A allowance	Limit LED current to keep total <=3 A

Sizing Implications

The 3 A input target is tight if all 32 RGBWW LEDs and ESP32 Wi-Fi peak simultaneously. Firmware current limiting is required for reliable operation from 3 A sources.
A 3 A PPTC must be checked carefully: PPTCs derate with temperature and can have enough resistance to cause LED voltage sag at high current.
Copper distribution should use layer 3 as a 5 V plane, wide top/bottom pours for local LED current, and many stitching vias.
Layer 2 should remain a solid ground plane except antenna and mechanical keepouts.
Bulk capacitance near entry is mandatory; add distributed 0.1 uF decoupling near LEDs and ICs plus local bulk capacitance around LED rings as layout permits.

LDO Thermal Check

TLV75733PDBVR dissipates approximately (5 V - 3.3 V) * I_3V3.

Table

I_3V3	Dissipation
250 mA	0.425 W
500 mA transient	0.85 W transient

A SOT-23-class 1 A LDO may run hot if ESP32 average current is high. Use generous copper on the LDO thermal node/ground where the package permits, verify package thermal limits from the datasheet, and consider a buck regulator or larger-package LDO if continuous Wi-Fi plus warm enclosure conditions exceed thermal margin.

Key Risks to Verify During Schematic/Layout

GPIO12 is an ESP32 strapping pin. The AHCT input and LED data network must not pull GPIO12 high at boot.
No USB-C connector is included in this locked spec despite earlier USB-C language; power enters through 5 V/GND pads.
Source current capability is not measured in this design; current limiting must be firmware-configured or provided by installation instructions.
Full 3 A operation requires careful plane/pour design, adequate connector pad sizing, and thermal review of the PPTC/MOSFET.

Summary
Power Tree
Load Estimate
Summed Current
Sizing Implications
LDO Thermal Check
Key Risks to Verify During Schematic/Layout