PCB Re-layout Routing

flux

I’ll move only the FPGA passives blocking U3’s camera-pin sides, keep their electrical groups intact, then rerun DRC and routing feasibility without routing.

flux

Moved FPGA decoupling capacitors C19–C29 outward to open the camera-pin fanout corridors and removed nine resulting stale traces.
  • All CAM1/CAM2 U3 pins now pass routing feasibility
  • No blocked camera nets
  • Overlaps, dangling traces, and outside-board components: 0
  • Board-wide airwires: 170
  • Only the informational exposed-pad via advisory remains
G

gavipk

Route all remaining J2/J3 camera signals to U3, then run DRC.

flux

I’ll route all remaining J2/J3 camera signals to U3 through the newly opened fanout corridors, then run DRC and report exact residual camera airwires or advisories.

flux

Routed four additional camera connections:
  • CAM1_XCLK_SRC
  • CAM2_XCLK_SRC
  • CAM1_PCLK
  • CAM1_VSYNC
Blocked after two attempts: CAM2_PCLK, CAM2_VSYNC, and CAM1_HREF; remaining camera buses were not safely reachable. DRC shows 0 overlaps, dangling traces, invalid layers, or outside-board components. Board-wide airwires decreased to 166.
Open camera corridors
Use narrower neckdowns
Inspect U3 congestion
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Schematic

Layout

3D View

Gowin Constraint Validation Notes
Static validation result
  • Checked actual U3 schematic nets against the QN88P physical pin names and package numbers, DS117 operating limits, and the UG803/UG119 mapping already captured in Architecture Validation.
  • No duplicate package-pin assignments were found in the actual connected U3 signals.
  • Bank 2 carries Camera 1 at 3.3 V; Bank 1 carries ULPI and most Camera 2 signals at 3.3 V; Bank 3 carries reference/config/JTAG/control signals at 3.3 V. U3 VCCIO1/2/3 and combined VCCX/VCCIO0 are tied to +3V3_BUCK; VCC is tied to +1V2_FPGA. These values satisfy DS117 recommended ranges.
  • Dedicated/global-clock capable assignments are: Camera 1 PCLK pin 35 GCLKT_4, Camera 1 XCLK source pin 36 GCLKC_4, ULPI 60 MHz pin 51 GCLKC_3, Camera 2 PCLK pin 52 GCLKT_3, and 24 MHz reference pin 10 GCLKT_6.
  • Clock-resource caveat: pins 51/52 are the complementary GCLKC_3/GCLKT_3 pair. Static pin capability is valid, but simultaneous use as independent ULPI and camera clocks still requires Gowin place-and-route acceptance.
  • Pins 53-62 are configuration-multiplexed. Their ULPI use is conditional on internal-flash AUTO BOOT and the USB3320 remaining reset/Hi-Z during configuration.
  • Pin 63 is RPLL_T_in; GPIO use is conditional on not consuming that dedicated PLL input.
  • JTAG pins 5-8 are preserved for JTAG. JTAGSEL_N, RECONFIG_N, MODE1 and MODE0 remain hardware straps, not ordinary RTL ports.
  • No schematic pin reassignment was made because the static review found no authoritative hard conflict.
Required external gate
The Gowin vendor toolchain is unavailable in this environment. The CST must be parsed against the exact installed device database for GW1NR-LV9QN88PC6/I5, then synthesized and placed to prove clock-resource legality and configuration-pin reuse.
Camera blocker retained
The purchased camera-module MPN and flex drawing remain unknown. Therefore 3.3 V DVP compatibility, pin numbering/contact-side orientation, cable geometry, and actuator access are not frozen by this validation.

  • Static validation result

  • Required external gate

  • Camera blocker retained