PCB Re-layout Routing

flux

Moved FPGA decoupling capacitors C19–C29 outward to open the camera-pin fanout corridors and removed nine resulting stale traces.
  • All CAM1/CAM2 U3 pins now pass routing feasibility
  • No blocked camera nets
  • Overlaps, dangling traces, and outside-board components: 0
  • Board-wide airwires: 170
  • Only the informational exposed-pad via advisory remains
gavipk

gavipk

Route all remaining J2/J3 camera signals to U3, then run DRC.

flux

I’ll route all remaining J2/J3 camera signals to U3 through the newly opened fanout corridors, then run DRC and report exact residual camera airwires or advisories.

flux

Routed four additional camera connections:
  • CAM1_XCLK_SRC
  • CAM2_XCLK_SRC
  • CAM1_PCLK
  • CAM1_VSYNC
Blocked after two attempts: CAM2_PCLK, CAM2_VSYNC, and CAM1_HREF; remaining camera buses were not safely reachable. DRC shows 0 overlaps, dangling traces, invalid layers, or outside-board components. Board-wide airwires decreased to 166.
Open camera corridors
Use narrower neckdowns
Inspect U3 congestion

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Architecture Validation
Executive Result
Reconciliation status (capture gate): BLOCKED. The two user attachments are requirement notes, not manufacturer-controlled drawings. They consistently specify a 24-pin, 0.5 mm, bottom-contact OV5640-class DVP module and the pin list below, but neither attachment identifies an orderable camera-module MPN or supplies its dimensional/electrical drawing. Therefore the camera pinout, 3.3 V I/O tolerance, flex contact-side orientation, VCM load, and module power are still assumptions and cannot be called exact. The exact FPGA production MPN GW1NR-LV9QN88PC6/I5 is a real QN88P orderable, but no terminal-bearing Flux library part exists. Per the no-placeholder requirement, schematic capture must not instantiate either item until the exact camera module is identified and a verified real FPGA part is approved/imported.
  • Power: Feasible from 5 V USB-C, but the earlier two-rail plan is incomplete. USB3320 requires a 1.8 V supply in addition to 3.3 V and 1.2 V. The preliminary peak estimate is about 2.49 W or 553-585 mA at 5 V, so operation cannot be guaranteed from a legacy 500 mA USB source.
  • USB bandwidth: 1280 x 480 YUV422 at 30 fps cannot fit in USB 2.0 High-Speed isochronous bandwidth. It requires 294.912 Mbit/s while the endpoint payload ceiling is 196.608 Mbit/s. Even 20 fps consumes the mathematical ceiling before UVC overhead. Use 15 fps uncompressed or compression.
  • FPGA capacity: The GW1NR-LV9QN88P has enough package I/O and memory for the proposed architecture. Estimated use is about 52 of 71 user I/O. BSRAM is ample for line buffers, and the integrated 64 Mbit PSRAM is ample for full frames.
Source Device Facts
GW1NR-LV9QN88P
  • 8,640 LUT4s and 6,480 flip-flops.
  • 468 Kbit BSRAM in 26 blocks.
  • 608 Kbit user flash.
  • QN88P includes 64 Mbit x16 PSRAM.
  • PSRAM rated to 166 MHz DDR332 with stated 664 MB/s bandwidth.
  • 20 hardware 18 x 18 multipliers and 2 PLLs.
  • 71 maximum user I/O in QN88P.
  • I/O distribution: Bank 1 = 25, Bank 2 = 23, Bank 3 = 23; Bank 0 has no user I/O in this package.
  • LV core supply: 1.14-1.26 V.
  • I/O-bank supplies: 1.14-3.6 V.
  • Auxiliary VCCX: 2.375-3.6 V.
USB3320
  • VBAT input: 3.1-5.5 V.
  • VDD33: 3.0-3.6 V, generated by its internal LDO when powered from VBAT.
  • VDD18: 1.6-2.0 V and must be supplied.
  • VDDIO: 1.6-3.6 V; use 3.3 V to match the FPGA ULPI bank.
  • High-Speed typical currents: 11.1 mA on 3.3 V circuitry, 29.4 mA on 1.8 V, and 5.9 mA on VDDIO.
  • VDD18 must be stable before VDDIO unless they are tied together.
OV5640
Bare-sensor datasheet values are not the same as the unknown 24-pin module values:
  • VGA 30 fps bare-sensor typical current: 30 mA analog plus 58 mA digital/output under the listed test conditions.
  • Product active-current headline: 140 mA.
  • Bare die requires 2.8 V analog, 1.5 V core, and 1.8/2.8 V I/O, but the supplied module description says it accepts 3.3 V and contains regulators.
  • The budget therefore uses 140 mA typical per module and a provisional 180 mA peak until the exact module is sourced and measured.
TPS62420
  • Input: 2.5-6 V.
  • Two adjustable buck outputs: OUT1 up to 600 mA and OUT2 up to 1000 mA.
  • Adjustable range starts at 0.6 V.
  • Efficiency up to 95%; 32 uA typical quiescent current with both converters idle in PFM.
Detailed Preliminary Power Budget
Assumptions Requiring Later Replacement
FPGA current is strongly dependent on synthesized resource use, clock rates, I/O toggle rates, and PSRAM activity. Until RTL is available for the Gowin power estimator, use this design envelope:
  • FPGA 1.2 V core: 250 mA typical, 450 mA peak.
  • FPGA 3.3 V I/O plus VCCX: 70 mA typical, 140 mA peak.
  • Each camera module: 140 mA typical, 180 mA peak from 3.3 V.
  • Miscellaneous 3.3 V loads: 20 mA typical, 40 mA peak.
  • USB3320 planning peak: 1.5 times its listed High-Speed typical power.
Rail Budget

Table

RailLoadTypicalPlanning peak
3.3 VCamera 1 module140 mA180 mA
3.3 VCamera 2 module140 mA180 mA
3.3 VFPGA I/O and VCCX70 mA140 mA
3.3 VClock, pull-ups, indicators, control20 mA40 mA
3.3 V subtotal370 mA540 mA
1.2 VFPGA core250 mA450 mA
1.2 V subtotal250 mA450 mA
1.8 VUSB3320 VDD1829.4 mA44.1 mA
3.3 V or internalUSB3320 VDDIO5.9 mA8.9 mA
5 V VBATUSB3320 internal 3.3 V sectionequivalent 7.3 mA at 5 Vequivalent 11.0 mA at 5 V
The calculated load totals, treating USB3320 rail power explicitly, are approximately:

Table

StateLoad power5 V current at 90%5 V current at 85%
Typical1.63 W362 mA384 mA
Planning peak2.49 W552 mA585 mA
Power Architecture Decision
  1. Use TPS62420 OUT2, the 1 A channel, for 3.3 V.
  2. Use TPS62420 OUT1, the 600 mA channel, for 1.2 V.
  3. Add a small 1.8 V LDO from 3.3 V for USB3320 VDD18. At about 44 mA peak its worst provisional dissipation is roughly (3.3 - 1.8) x 0.044 = 66 mW.
  4. Power USB3320 VBAT directly from protected 5 V VBUS and use its internal VDD33 regulator only for itself.
  5. Power USB3320 VDDIO from 3.3 V to keep ULPI at 3.3 V LVCMOS.
  6. Sequence or hold the PHY in reset until 1.8 V is valid before enabling its 3.3 V VDDIO interface.
Regulator Margin Assessment
  • 3.3 V planning peak of 540 mA should be assigned to the TPS62420 1 A channel, leaving useful current margin.
  • 1.2 V planning peak of 450 mA fits the 600 mA channel but has only 150 mA provisional margin. Re-run the Gowin power estimator after place-and-route; change the regulator if the calculated peak exceeds about 500 mA.
  • Do not design around a guaranteed 500 mA source. The host must advertise sufficient Type-C current, or the design must reduce peak load through camera/FPGA sequencing.
  • Size the VBUS path for at least the planning peak plus margin. A lossy 500 mA PTC is inappropriate because it can trip or cause excessive voltage drop.
  • MLCC nominal capacitance should be at least twice the required effective capacitance to account for DC-bias loss.
USB 2.0 High-Speed Bandwidth Validation
Raw Stream
YUV422 uses 16 bits per pixel.

Table

Stitched modeRaw rateRaw payload
1280 x 480 at 30 fps294.912 Mbit/s36.864 MB/s
1280 x 480 at 20 fps196.608 Mbit/s24.576 MB/s
1280 x 480 at 15 fps147.456 Mbit/s18.432 MB/s
Isochronous Limit
A USB 2.0 High-Speed high-bandwidth isochronous endpoint can carry at most three 1024-byte transactions in each 125 us microframe:
3 x 1024 bytes x 8000 microframes/s = 24.576 MB/s = 196.608 Mbit/s
Consequences:
  • 30 fps requires 150% of the endpoint payload ceiling and is impossible.
  • 20 fps requires 100% of the ceiling before UVC payload headers, frame markers, host scheduling, and implementation gaps, so it is not a viable product mode.
  • 15 fps uses 75% and leaves 25% mathematical payload headroom. This is the recommended uncompressed validation mode.
  • A bulk UVC transport might deliver more average payload on a quiet bus but does not remove host-controller, Android compatibility, latency, and no-bandwidth-guarantee risks. It should not be the baseline architecture without a phone-specific proof.
Required Video Decision
Recommended advertised modes:
  1. Baseline: 1280 x 480 YUV422 at 15 fps over High-Speed isochronous.
  2. Fallback: 1280 x 480 YUV422 at 10 fps.
  3. Performance target: 1280 x 480 at 30 fps using MJPEG generated by the OV5640 sensors or a verified FPGA compression pipeline.
The OV5640 has a JPEG engine, so the preferred 30 fps path is to investigate synchronized per-camera JPEG output and host-side composition, or a compatible compressed stitching architecture. Byte-wise concatenation of two JPEG streams does not form one valid stitched JPEG; a true stitched compressed frame requires decode/re-encode or a different application transport.
FPGA I/O Capacity
Conservative Allocation

Table

FunctionEstimated user I/O
Camera 1 D[7:0], PCLK, HREF, VSYNC11
Camera 2 D[7:0], PCLK, HREF, VSYNC11
Two XCLK outputs2
Two RSTB and two PWDN controls4
Two independent SCCB buses4
USB3320 ULPI D[7:0], CLK, DIR, NXT, STP12
USB3320 RESETB and optional interrupt/control2
FPGA reference clock1
Power-good/regulator controls2
Status/debug GPIO allowance3
Estimated total52
  • QN88P provides 71 maximum user I/O, leaving about 19 pins of gross margin.
  • Dedicated configuration/JTAG pins should be verified in the exact pin table and not casually repurposed.
  • The real constraint is bank assignment, not total count. Camera buses should each be kept within one 3.3 V bank where practical, and the 3.3 V ULPI bus should occupy a coherent bank group.
  • All three populated user banks may run at 3.3 V, which is compatible with the provisional camera module and USB3320 VDDIO plan.
  • Confirm whether any camera module output is actually limited to 2.8 V or 1.8 V before setting bank voltages.
FPGA Memory Capacity
Line Buffering

Table

BufferBits
One 640-pixel YUV422 input line10,240
Two input lines20,480
One 1280-pixel stitched output line20,480
Total conservative line buffering40,960 bits
The FPGA has 468 Kbit BSRAM, so this consumes about 8.8% before FIFO overhead. There is ample BSRAM for line FIFOs, clock-domain crossing, UVC packet buffering, and control tables.
Full Frames
  • One 640 x 480 YUV422 frame: 4,915,200 bits = 614,400 bytes.
  • Two input frames: 9,830,400 bits = 1,228,800 bytes.
  • QN88P PSRAM: 64 Mbit = 8 MiB nominal capacity.
  • Two full input frames consume about 15% of PSRAM.
The stated PSRAM bandwidth is 664 MB/s, far above the roughly 74 MB/s minimum aggregate traffic for writing two raw inputs and reading one stitched raw output at 30 fps. Arbitration efficiency and controller implementation still require RTL testing, but external memory capacity and headline bandwidth are not blockers.
Logic-Capacity Qualification
The device has 8,640 LUT4s, 6,480 FFs, 20 multipliers, and 2 PLLs. Capture, line FIFOs, stitching, ULPI, descriptors, and a basic UVC packet engine are plausible, but logic fit cannot be guaranteed from the datasheet alone. Completion criterion is a Gowin synthesis and place-and-route report with:
  • LUT and FF utilization below 80%.
  • BSRAM utilization below 80%.
  • Both camera PCLK domains and ULPI timing closed with positive slack.
  • At least one PLL left available only if the final clock plan requires it; otherwise both may be allocated.
  • A Gowin power-estimator report generated from routed activity data.
Final Architecture Status

Table

GateStatusDecision
Power capacityConditional passAdd 1.8 V rail; require more than legacy 500 mA capability or enforce sequencing
USB 30 fps uncompressedFailUse 15 fps YUV422 or compression
FPGA package I/OPass with bank-planning conditionAbout 52 of 71 I/O estimated
FPGA line-buffer memoryPassAbout 41 Kbit of 468 Kbit BSRAM
FPGA full-frame memoryPassIntegrated 64 Mbit PSRAM is sufficient
FPGA logic and dynamic powerPending RTLMust be proven by synthesis, timing, and power reports
1.8 V Regulator Selection — Frozen for Schematic Capture
Selected MPN: Texas Instruments TPS79318DBVR (commercial active device; fixed 1.8 V, 200 mA, DBV/SOT-23-5). The Flux library contains the pin-compatible TPS79318-EP entry, part UID 70298634-d0a0-4d89-b6e2-bd9a2d6bb9c0; use that entry only after confirming its orderable MPN property, or source the active TPS79318DBVR entry by exact MPN at capture time. No component has been added in this planning phase.
Sources: TI TPS793 datasheet Rev. N and TI TPS79318DBVR product page (ACTIVE); Flux library search; Microchip USB3320 datasheet DS00001792; Gowin UG803/UG119 pinout guides.
Electrical validation

Table

ItemValidation
LoadUSB3320 VDD18 is 29.4 mA typical; planning peak is 44.1 mA (1.5x).
Current margin200 mA rating gives 155.9 mA / 78% unused at the planning peak; peak is 22.1% of rating.
Input/headroom3.3 V nominal input is 1.5 V above 1.8 V. TPS793 minimum operating input is 2.7 V, so regulation is retained for a 3.3 V rail down to 2.7 V. This constraint, not dropout, is the limiting headroom.
DropoutFamily dropout is about 112 mV typical at 200 mA for the 3.0 V member; the 44.1 mA load is far below full load. Available headroom is therefore ample. Exact TPS79318 dropout over temperature is not separately guaranteed in the retrieved table; enforce VIN >= 2.8 V for the guaranteed 1.8 V output-accuracy condition.
AccuracyTPS79318: 1.764-1.836 V across 0-200 mA and 2.8-5.5 V, inside USB3320 VDD18 range 1.6-2.0 V.
Dissipation(3.3-1.8)*44.1mA = 66.15mW planning peak; typical is 44.1 mW. With high-K-board RthetaJA 178.3 C/W, estimated rise is about 11.8 C at planning peak; low-K bound is about 16.9 C. Thermally comfortable.
Stability/capsPlace >=0.1 uF ceramic at IN and >=2.2 uF effective ceramic at OUT, each directly at the IC. Select 4.7 uF nominal X7R/X5R at OUT so effective capacitance remains >=2.2 uF after DC-bias/tolerance. Add 0.01 uF low-leakage ceramic from BYPASS to GND for low noise.
Startup/noise tradeTypical startup is about 100 us with 0.01 uF BYPASS (family characterization); larger BYPASS lowers noise but slows startup. 0.01 uF is the baseline.
EnableEN high enables, EN low shuts down; VIH >=2.0 V, VIL =6.3 V, X7R/X5R ceramic (exceeds 0.1 uF minimum).
  • C_LDO18_OUT: 4.7 uF nominal, >=6.3 V, X7R/X5R ceramic; verify >=2.2 uF effective at 1.8 V.
  • C_LDO18_BYP: 10 nF low-leakage ceramic.
  • R_LDO18_EN_PD: 100 kohm pull-down if FPGA-controlled.
  • Nets: +3V3_BUCK, +1V8_USBPHY, LDO18_EN, PG_1V8, USBPHY_RESETB, GND.
Sequencing decision
  1. Bring up 1.2 V and 3.3 V bucks with cameras disabled and USB3320 held in reset.
  2. Assert LDO18_EN; wait at least 0.5 ms (more than the characterized ~100 us startup, subject to final supervisor timing).
  3. Confirm PG_1V8 from a supervisor or elapsed-time qualification.
  4. Apply/enable USB3320 VDDIO at 3.3 V only after VDD18 is stable, as required by the USB3320 sequencing rule; VBAT may already be present from protected VBUS.
  5. Release USBPHY_RESETB, then enable cameras one at a time to limit USB-source inrush.
USB3320 VDDIO sequencing implementation — completed
  • U5 = TI TPS3808G18DBVR (SOT-23-6) monitors +1V8_USBPHY on both VDD and SENSE. Its fixed threshold is 1.67 V with ±1.5% worst-case accuracy and 1-2.5% hysteresis.
  • U5 CT is intentionally open, selecting the datasheet-guaranteed 12-28 ms reset delay (20 ms typical) after the 1.8 V rail crosses threshold. MR is intentionally unused; its internal 70-90 kohm pull-up keeps it inactive.
  • U6 = Vishay SiP32431DR3 (SC-70-6), a 1 A active-high load switch with reverse blocking. It gates only USB3320 VDDIO; the FPGA and all other +3V3_BUCK loads remain directly powered.
  • R28 10 kohm pulls PG_1V8 / U6 ON toward +1V8_USBPHY; R29 100 kohm pulls it to ground. With U5 released, the divider produces about 1.64 V nominal, above U6's guaranteed 1.5 V VIH at 3.3 V input. While U5 asserts RESET, its <=0.4 V VOL is below U6's 0.6 V VIL maximum. Below the supervisor's valid operating region, the collapsing 1.8 V pull-up plus R29 guarantees ON returns low instead of floating.
  • C34 100 nF decouples U5; C35 100 nF bypasses U6 input. Existing C5 100 nF remains directly on the new switched rail USBPHY_VDDIO_3V3 at U1 VDDIO.
  • USB3320 requires VDD18 stable before VDDIO and allows 1.6-3.6 V VDDIO. Its active VDDIO current is only 5.9 mA typical; U6's 1 A rating and reverse blocking provide ample margin and prevent backfeed during shutdown.
  • Timing basis: TPS79318 worst listed family startup is 500 us for the new die; U5 then waits at least 12 ms after the monitored rail exceeds its 1.67 V threshold before enabling U6. U6 adds controlled turn-on (about 100-180 us), so VDD18 is established well before VDDIO reaches 3.3 V.
Exact Proposed GW1NR-9 QN88P Pin Allocation
Package-pin numbering follows authoritative Gowin GW1NR-9 pinout guide UG803E / package guide UG119. All user banks are planned at 3.3 V. This is a proposed constraint set; clock routing and configuration-pin reuse must be checked in the exact installed Gowin EDA device database before schematic freeze.
Source reconciliation and corrections
  • Attachment 1 supplies architecture assumptions only. Its claim that 1280 x 480 YUV422 at 30 fps fits USB HS is superseded by the endpoint calculation in this file; 15 fps is the uncompressed baseline.
  • Attachment 2 supplies the 24-pin camera table, but calls the module only “standard OV5640”; that is not an exact procurement identity. The table is retained as a provisional interface contract, not a verified module pinout.
  • Gowin UG119 confirms QN88P is QFN-88P, 0.4 mm pitch; production orderables append speed/grade, with GW1NR-LV9QN88PC6/I5 confirmed as an orderable QFN-88 device.
  • UG119 confirms QN88P power pins: VCC pins 1, 22, 45, 66; VCCIO1 pin 58; VCCIO2 pins 23 and 44; VCCIO3 pin 12; combined VCCX/VCCIO0 pins 64, 67, 78; VSS pins 2, 21, 24, 43, 46, 65. All VCCIO banks at 3.3 V are electrically allowed only if the camera module really presents 3.3 V-compatible I/O. VCCX must also be 3.3 V.
  • Pins 51 and 52 are the complementary GCLKC_3/GCLKT_3 pair. Assigning ULPI_CLK and CAM2_PCLK to the same pair remains a clock-resource/tool-fit risk; it is not considered validated until Gowin P&R accepts both clocks.
  • Pins 53–62 are configuration-multiplexed. Their post-boot use for ULPI is conditional on internal-flash boot mode and the PHY remaining reset/Hi-Z during configuration.
  • Pins 4–9 and 87–88 remain reserved for JTAG/configuration. They are not counted as spares.
Gowin CST-style proposed allocation
Tcl
IO_LOC "CAM1_D9" 25; IO_PORT "CAM1_D9" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_D8" 26; IO_PORT "CAM1_D8" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_D7" 27; IO_PORT "CAM1_D7" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_D6" 28; IO_PORT "CAM1_D6" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_D5" 29; IO_PORT "CAM1_D5" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_D4" 30; IO_PORT "CAM1_D4" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_D3" 31; IO_PORT "CAM1_D3" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_D2" 32; IO_PORT "CAM1_D2" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_HREF" 33; IO_PORT "CAM1_HREF" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_VSYNC" 34; IO_PORT "CAM1_VSYNC" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_PCLK" 35; IO_PORT "CAM1_PCLK" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_XCLK" 36; IO_PORT "CAM1_XCLK" IO_TYPE=LVCMOS33 DRIVE=8;
IO_LOC "CAM1_RSTB" 37; IO_PORT "CAM1_RSTB" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_PWDN" 38; IO_PORT "CAM1_PWDN" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_SCCB_SCL" 39; IO_PORT "CAM1_SCCB_SCL" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_LOC "CAM1_SCCB_SDA" 40; IO_PORT "CAM1_SCCB_SDA" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_LOC "CAM1_LOCK_STATUS" 41; IO_PORT "CAM1_LOCK_STATUS" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_LOCK_STATUS" 42; IO_PORT "CAM2_LOCK_STATUS" IO_TYPE=LVCMOS33;
IO_LOC "BUCK33_EN" 17; IO_PORT "BUCK33_EN" IO_TYPE=LVCMOS33;
IO_LOC "BUCK12_EN" 18; IO_PORT "BUCK12_EN" IO_TYPE=LVCMOS33;
IO_LOC "CAM1_PWR_EN" 19; IO_PORT "CAM1_PWR_EN" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_PWR_EN" 20; IO_PORT "CAM2_PWR_EN" IO_TYPE=LVCMOS33;
IO_LOC "VCM_PWR_EN" 47; IO_PORT "VCM_PWR_EN" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D9" 62; IO_PORT "CAM2_D9" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D8" 63; IO_PORT "CAM2_D8" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D7" 68; IO_PORT "CAM2_D7" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D6" 69; IO_PORT "CAM2_D6" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D5" 70; IO_PORT "CAM2_D5" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D4" 71; IO_PORT "CAM2_D4" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D3" 72; IO_PORT "CAM2_D3" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_D2" 73; IO_PORT "CAM2_D2" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_HREF" 74; IO_PORT "CAM2_HREF" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_VSYNC" 75; IO_PORT "CAM2_VSYNC" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_PCLK" 52; IO_PORT "CAM2_PCLK" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_XCLK" 77; IO_PORT "CAM2_XCLK" IO_TYPE=LVCMOS33 DRIVE=8;
IO_LOC "ULPI_D0" 48; IO_PORT "ULPI_D0" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_D1" 49; IO_PORT "ULPI_D1" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_D2" 50; IO_PORT "ULPI_D2" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_D3" 53; IO_PORT "ULPI_D3" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_D4" 54; IO_PORT "ULPI_D4" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_D5" 55; IO_PORT "ULPI_D5" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_D6" 56; IO_PORT "ULPI_D6" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_D7" 57; IO_PORT "ULPI_D7" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_CLK" 51; IO_PORT "ULPI_CLK" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_DIR" 76; IO_PORT "ULPI_DIR" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_NXT" 59; IO_PORT "ULPI_NXT" IO_TYPE=LVCMOS33;
IO_LOC "ULPI_STP" 60; IO_PORT "ULPI_STP" IO_TYPE=LVCMOS33;
IO_LOC "USBPHY_RESETB" 61; IO_PORT "USBPHY_RESETB" IO_TYPE=LVCMOS33;
IO_LOC "FPGA_REFCLK" 10; IO_PORT "FPGA_REFCLK" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_RSTB" 11; IO_PORT "CAM2_RSTB" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_PWDN" 13; IO_PORT "CAM2_PWDN" IO_TYPE=LVCMOS33;
IO_LOC "CAM2_SCCB_SCL" 14; IO_PORT "CAM2_SCCB_SCL" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_LOC "CAM2_SCCB_SDA" 15; IO_PORT "CAM2_SCCB_SDA" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_LOC "LDO18_EN" 16; IO_PORT "LDO18_EN" IO_TYPE=LVCMOS33;
IO_LOC "PG_3V3" 79; IO_PORT "PG_3V3" IO_TYPE=LVCMOS33;
IO_LOC "PG_1V2" 80; IO_PORT "PG_1V2" IO_TYPE=LVCMOS33;
IO_LOC "PG_1V8" 81; IO_PORT "PG_1V8" IO_TYPE=LVCMOS33;
IO_LOC "USBPHY_STATUS" 82; IO_PORT "USBPHY_STATUS" IO_TYPE=LVCMOS33;
IO_LOC "JTAG_TMS" 5;
IO_LOC "JTAG_TCK" 6;
IO_LOC "JTAG_TDI" 7;
IO_LOC "JTAG_TDO" 8;
JTAGSEL_N pin 4, RECONFIG_N pin 9, MODE1 pin 87, and MODE0 pin 88 are hardware straps/test nodes rather than ordinary RTL ports in the proposed CST. Exact strap states must be taken from the selected internal-flash boot mode in the installed Gowin tool documentation. Do not copy the provisional PULL_MODE or DRIVE attributes into production constraints without tool acceptance and signal-integrity review.

Table

Package pinBankGowin pin functionProposed net
252IOB8ACAM1_D9
262IOB8BCAM1_D8
272IOB11ACAM1_D7
282IOB11BCAM1_D6
292IOB13ACAM1_D5
302IOB13BCAM1_D4
312IOB15ACAM1_D3
322IOB15BCAM1_D2
332IOB23ACAM1_HREF
342IOB23BCAM1_VSYNC
352IOB29A/GCLKT_4CAM1_PCLK
362IOB29B/GCLKC_4CAM1_XCLK
372IOB31ACAM1_RSTB
382IOB31BCAM1_PWDN
392IOB33ACAM1_SCCB_SCL
402IOB33BCAM1_SCCB_SDA
412IOB41ACAM1_LOCK_STATUS
422IOB41BCAM2_LOCK_STATUS
172IOB2ABUCK33_EN
182IOB2BBUCK12_EN
192IOB4ACAM1_PWR_EN
202IOB4BCAM2_PWR_EN
472IOB43BVCM_PWR_EN
621IOR11A/MI/D7CAM2_D9
631IOR5A/RPLL_T_inCAM2_D8
681IOT42BCAM2_D7
691IOT42ACAM2_D6
701IOT41BCAM2_D5
711IOT41ACAM2_D4
721IOT39BCAM2_D3
731IOT39ACAM2_D2
741IOT38BCAM2_HREF
751IOT38ACAM2_VSYNC
521IOR17A/GCLKT_3CAM2_PCLK
771IOT37ACAM2_XCLK
481IOR24BULPI_D0
491IOR24AULPI_D1
501IOR22BULPI_D2
531IOR15B/DOUT/WE_NULPI_D3
541IOR15A/DIN/CLKHOLD_NULPI_D4
551IOR14B/SSPI_CS_N/D0ULPI_D5
561IOR14A/SO/D1ULPI_D6
571IOR13A/FASTRD_N/D3ULPI_D7
511IOR17B/GCLKC_3ULPI_CLK
761IOT37BULPI_DIR
591IOR12B/MCLK/D4ULPI_NXT
601IOR12A/MCS_N/D5ULPI_STP
611IOR11B/MO/D6USBPHY_RESETB
103IOL15A/GCLKT_6FPGA_REFCLK
113IOL16BCAM2_RSTB
133IOL21BCAM2_PWDN
143IOL22BCAM2_SCCB_SCL
153IOL25BCAM2_SCCB_SDA
163IOL26BLDO18_EN
793IOT12BPG_3V3
803IOT12APG_1V2
813IOT11BPG_1V8
823IOT11AUSBPHY_STATUS
53IOL11A/TMSJTAG_TMS (dedicated use)
63IOL11B/TCKJTAG_TCK (dedicated use)
73IOL12B/TDIJTAG_TDI (dedicated use)
83IOL13A/TDOJTAG_TDO (dedicated use)
43IOL5A/JTAGSEL_N/LPLL_T_inJTAGSEL_N strap/test pad
93IOL13B/RECONFIG_NRECONFIG_N/test pad
873IOT6B/MODE1MODE1 strap
883IOT5A/MODE0MODE0 strap
Bank and count reconciliation

Table

BankQN88P available user-capable pinsAssigned application I/ODedicated/config reservedSpare
1252500
2232300
323108 (TMS/TCK/TDI/TDO, JTAGSEL_N, RECONFIG_N, MODE0, MODE1)5
Total715885
The 71 figure counts multiplexed JTAG/configuration-capable pads as user-capable I/O. This design deliberately reserves eight of them for dedicated/configuration use. Pin 3 plus pins 83-86 are the five current spares. No package pin is duplicated in the table. Power pins (VCC, VCCIO, VSS) and package-grounded MODE2 are not counted as signals.
Mandatory Gowin-tool validation flags
  • Verify the exact orderable device string GW1NR-LV9QN88PC6/I5 (or final speed/temperature suffix) and import this table into a Gowin .cst; the tool database is the final authority.
  • Confirm both camera PCLK choices and ULPI_CLK can use global clock resources simultaneously; pins 35, 51, and 52 are clock-capable, but 51/52 are a complementary pair and require clock-resource validation.
  • Pins 53-62 are configuration-multiplexed. Confirm they become ordinary Bank-1 I/O after internal-flash boot with the selected MODE straps and that ULPI does not drive them during configuration.
  • Confirm pin 63 RPLL_T_in may be used as ordinary GPIO when the right PLL input is unused.
  • Confirm JTAG remains enabled by the JTAGSEL_N strap and that MODE0/MODE1 straps select internal-flash boot. MODE2 is package-grounded.
  • Bank 1 is fully allocated; any tool conflict must be resolved by moving low-speed controls/status to Bank 3, not by splitting ULPI data timing indiscriminately.
  • The exact camera modules must be proven 3.3 V tolerant before locking all VCCIO banks to 3.3 V.
Pre-Capture Block Plan and Remaining Risks
  1. USB-C/VBUS protection: receptacle, CC pull-downs, ESD, protected 5 V distribution, source-current policy.
  2. Dual buck: TPS62420 3.3 V/1.2 V rails, sequencing, effective capacitance and rail-specific current proof.
  3. USB PHY: USB3320 VBAT from protected 5 V, VDDIO 3.3 V, VDD18 from TPS79318, reset qualification, ULPI and USB support network.
  4. FPGA: QN88P power/decoupling, configuration straps, JTAG, oscillator, bank supplies, PSRAM constraints.
  5. Camera interfaces: two FPCs, local filtering/decoupling, separate SCCB, reset/power-down, 24 MHz XCLK, optional VCM branches.
  6. Supervision/status: rail PG generation (external supervisor because neither TPS79318 nor the provisional buck plan guarantees all required PG outputs), deterministic reset, camera/PHY enables.
Remaining pre-capture risks: exact camera-module voltage/pinout; final Gowin .cst acceptance and clock-resource placement; TPS62420 startup/order and effective-capacitance design; choice of external supervisor/PG topology; USB3320 exact package variant and checklist; USB source-current negotiation; and RTL timing/resource/power proof. Schematic capture remains intentionally unstarted.

  • Executive Result

  • Source Device Facts

  • GW1NR-LV9QN88P

  • USB3320

  • OV5640

  • TPS62420

  • Detailed Preliminary Power Budget

  • Assumptions Requiring Later Replacement

  • Rail Budget

  • Power Architecture Decision

  • Regulator Margin Assessment

  • USB 2.0 High-Speed Bandwidth Validation

  • Raw Stream

  • Isochronous Limit

  • Required Video Decision

  • FPGA I/O Capacity

  • Conservative Allocation

  • FPGA Memory Capacity

  • Line Buffering

  • Full Frames

  • Logic-Capacity Qualification

  • Final Architecture Status

  • 1.8 V Regulator Selection — Frozen for Schematic Capture

  • Electrical validation

  • Required 1.8 V support parts and nets

  • Sequencing decision

  • USB3320 VDDIO sequencing implementation — completed

  • Exact Proposed GW1NR-9 QN88P Pin Allocation

  • Source reconciliation and corrections

  • Gowin CST-style proposed allocation

  • Bank and count reconciliation

  • Mandatory Gowin-tool validation flags

  • Pre-Capture Block Plan and Remaining Risks

SentryCase

SentryCase thumbnail
Dual OV5640-class DVP camera to USB 2.0 High-Speed UVC interface using a Gowin GW1NR-9 FPGA and USB3320 ULPI PHY.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$8.86–$11.11

Digi-Key

$0.35

HQonline

$3.02–$3.12

LCSC

$10.82–$10.95

Mouser

$15.48–$23.38

TME

$0.92

Verical

$20.60–$26.07

Controls