Your topology is solid, and your placement choices are good. With a few checks you’ll keep the ADC and audio clean.
Power and grounds
Keep 3V3_A generated on the main board through the existing Ferrite Bead (600 Ω typ at 100 MHz is fine). Verify the bead’s DC resistance and current rating vs total analog load; add post‑bead decoupling at the entry: at least one 10 uF Capacitor in parallel with a 100 nF Capacitor, placed tight to the bead’s output.
Single‑point AGND–DGND tie near the bead is correct. Don’t rejoin grounds on the daughter board.
Export both rails to the daughter: 3V3_A+AGND only for pots and any analog/bias networks; 3V3+DGND for buttons/switches/LEDs. Interleave ground pins in the connector so each sensitive line has a close return.
STM32H743 ADC/pot interface
Excite pots ratiometrically from 3V3_A to AGND so readings track the ADC’s reference/supply.
At each ADC pin, add a small RC for anti‑aliasing, but size it with the ADC’s acquisition time in mind. The series R forms a DC error with the ADC bias current (Verror = Ibias × R) and slows the sample capacitor’s charging; keep series R modest (for example a 1 kΩ Resistor or less) and adjust sampling cycles accordingly. Avoid fixed “rules of thumb”; compute from Tacq and your effective source impedance.
If you use high‑value pots (e.g., 50–100 kΩ), consider buffering or lowering value to keep Rsource within what your sampling time can settle.
Audio path across the connector
AC‑coupling cap on the daughter near the board‑to‑board transition is fine. Ensure the receive‑side bias network and input resistor are on the main board and tight to the op‑amp input so the high‑pass pole is controlled locally and the return current flows right next to the amplifier reference.
Give the audio signal a ground‑adjacent pin in the connector (or route as a tight pair with a dedicated AGND pin next to it). Keep it physically separated from fast digital edges on the pinout.
Add low‑cap ESD at the connector for exposed analog lines, shunted to AGND, for example a small TVS Diode per line.
Noise containment and contingencies
If residual switching ripple leaks through, you can sharpen the post‑bead network (add a small HF cap like 1–10 nF right at VDDA/VREF+ in addition to 100 nF) or, where SNR is critical, feed the most sensitive analog block from a low‑noise LDO after the bead (high PSRR in your switching frequency band).
Place 4.7–10 uF plus 100 nF right after the connector on both rails (3V3_A–AGND and 3V3–DGND) on the daughter to stiffen local loads.
For any digital lines crossing boards, a small series resistor (22–51 Ω) near the driver can tame edges and crosstalk.
Sanity check summary
Yes: bring both 3V3_A/AGND and 3V3/DGND to the daughter; keep them separate there; single ground tie on main.
Yes: pots and any analog biasing should live on 3V3_A; buttons/switches on 3V3.
Yes: AC‑coupling near the transition is fine; ensure the receiver bias/returns live right at the main‑board op‑amp.
If you share pot values, intended ADC sampling time/clock, and connector length/pinout, I can size the RCs and sampling cycles precisely and suggest any tweaks to the pin assignment.