Fixing Missing Routed Traces
Thought for 50 sec
This error means Flux sees pads on the same net that are not physically connected by routed copper. That is exactly what the Airwires check reports: missing routed traces between pads in a net
For your specific case:
- ADHESION_1
P1is on the Top layer - ADHESION_2
P1is also on the Top layer - Both
P1pads are assigned to the same net, +BAT_RAW - So the fix is to route copper between those two pads, or remove/change the net assignment if they were not meant to be connected
What to do:
- In PCB view, select the airwire for
+BAT_RAWbetween ADHESION_1 and ADHESION_2. - Route a trace on the Top layer from
P1toP1. - Recheck the review.
Important:
- Your layout has plenty of board space, so this looks like a straightforward missing route, not a congestion problem.
- The project currently has many Airwires errors, not just this one, so fixing these two pads may clear only one of many unrouted nets.
If
+BAT_RAW on those two pads was accidental, then the real fix is on the schematic side:- disconnect or rename that net so they are no longer both on
+BAT_RAW.
If you want, I can inspect whether ADHESION_1 and ADHESION_2 are supposed to be on
+BAT_RAW, and tell you whether to route them or change the net.Inspect net intent
Check other airwires
Review +BAT_RAW path
Refine this doc
Ask about this doc
Design Notes
Approved Module
- Selected module: ESP32-S3-WROOM-1-N16R8
- Manufacturer: Espressif Systems
- Memory: 16 MB Flash, 8 MB PSRAM
- Package: SMD module, 25.5 mm x 18.0 mm
- Reason for approval: exceeds the minimum requirement of 8 MB Flash and 8 MB integrated PSRAM while staying in the required ESP32-S3-WROOM-1 family.
Interface Compatibility Review
- Schematic state: empty
- Layout state: empty
- Compatibility result: no existing power, programming, RF, or peripheral conflicts are present.
- Integration baseline: module can be adopted as the primary processing and wireless subsystem.
Required Electrical Interfaces
- 3.3 V main supply
- GND reference
- EN / CHIP_PU with 10k pull-up to 3.3 V and 100 nF to GND
- GPIO0 / BOOT access so the line is HIGH for normal boot and can be driven LOW for download mode
- Native USB D+ and D- or UART0 programming access reserved
- Local 100 nF decoupling at the module supply input, plus bulk rail capacitance in the future power stage
RF and Layout Requirements
- Use the integrated PCB antenna version only
- Place module at the board edge
- Keep all copper, traces, planes, and components out of the antenna keepout region
- Maintain solid ground reference under the module body except the antenna keepout area
- Keep noisy switching regulators and high current loops away from the antenna end of the module
Acceptance Criteria
- Approved variant remains ESP32-S3-WROOM-1-N16R8 unless requirements change
- Memory remains at or above 8 MB Flash and 8 MB PSRAM
- Future schematic must include EN pull-up and BOOT access
- Future layout must honor antenna keepout and edge placement
- Future programming interface must reserve native USB or UART access
Programming Header Baseline
- Add a dedicated 4-pin programming header for direct firmware download and recovery access
- Header signal set is TX0, RX0, EN, and BOOT
- Use a standard 1x4, 2.54 mm through-hole header footprint for accessibility during bring-up
- Header pins shall be clearly labeled in schematic and kept accessible from the board edge during layout
Current Integration State
- U1 is the approved ESP32-S3-WROOM-1-N16R8 module instance in the schematic baseline
- J1 is the dedicated 4-pin programming header instance in the schematic baseline
- Next required step is explicit pin mapping from U1 UART0 and control pins to J1 pins
- PCB baseline must add an all-layer antenna keep-out rule tied to the future ESP32 antenna zone
Implemented Signal Mapping
- U1 TXD0 is routed to J1 Pin 1 on net UART0_TX0
- U1 RXD0 is routed to J1 Pin 2 on net UART0_RX0
- U1 EN is routed to J1 Pin 3 on net ESP_EN
- U1 IO0 is routed to J1 Pin 4 on net ESP_BOOT
PCB Keep-Out Baseline
- Maintain an antenna exclusion region at the ESP32 antenna end with no copper, traces, polygons, or component placement on any copper layer
- Keep the module placed at a board edge with the antenna facing outward
- Keep the programming header accessible from a board edge separate from the antenna edge when possible
Power Architecture Decision
- USB-C 5 V input feeds a BQ24075 charger and power-path device
- A single-cell 3.7 V nominal LiPo connects through a 2-pin JST-PH battery connector
- The BQ24075 OUT node is used as the downstream system rail so the board can run while charging
- The system rail feeds a TPS62840 buck regulator configured for 3.3 V output to power the ESP32-S3 and future sensors
- This architecture was chosen because the power-path output avoids load interruption during USB plug and unplug events
BQ24075 Implementation Notes
- Selected device: BQ24075RGTT
- Required BAT bypass capacitor: 4.7 µF to 47 µF ceramic, use 4.7 µF minimum baseline
- Typical application uses 1 µF on IN, 4.7 µF on OUT, and 4.7 µF on BAT
- CE is active low and must not be left unconnected
- TS expects a 10 kΩ NTC thermistor; when battery temperature monitoring is not used, connect a 10 kΩ resistor from TS to VSS
- EN1 and EN2 must not be left unconnected
- SYSOFF tied to GND so the system path stays enabled by default
- ILIM resistor programs maximum input current using IIN-MAX = KILIM / RILIM, where KILIM = 1550 AΩ
- ISET resistor programs charge current using RISET = KISET / ICHG, where KISET = 890 AΩ
- Baseline charge-current target for this design: 0.8 A using approximately 1.13 kΩ on ISET
- Baseline resistor-programmed input limit target: about 1.3 A using approximately 1.18 kΩ on ILIM
- CHG and PGOOD are available as open-drain status outputs for future LEDs or MCU monitoring
TPS62840 Implementation Notes
- Selected device: TPS62840DLCR
- The converter is configured using a single resistor from VSET to GND
- Supported output range includes 3.3 V in 100 mV steps
- Required baseline externals: 4.7 µF input capacitor, 2.2 µH inductor, 10 µF X5R or X7R output capacitor
- VOS connects to the regulated 3.3 V node after the inductor
- MODE tied to GND for default power-save operation
- STOP tied to GND for normal operation
- Use an E96 1% resistor for VSET programming
USB-C Power Input Notes
- Use a power-only USB-C receptacle exposing VBUS, GND, CC1, and CC2
- Add 5.1 kΩ pull-down resistors from CC1 and CC2 to GND so the port advertises as a 5 V sink
- Place bulk capacitance near the USB-C VBUS entry and keep the VBUS path short to the charger IN pin
Implemented Power Components
- J2 is the 2-pin JST-PH battery connector
- J3 is the USB-C charging connector
- U2 is the BQ24075 charger and power-path IC
- IC1 is the TPS62840 3.3 V buck regulator
- Support passives are R1 to R6, C1 to C7, and L1
Implemented Power Net Mapping
- USB_5V: J3 VBUS pins to C1, C2, and U2 IN
- BAT: J2 positive terminal to U2 BAT pins and C4
- SYS: U2 OUT pins to IC1 VIN and EN, plus C3 and C5
- 3V3: IC1 output through L1 to U1 3V3, C6, and C7
- GND: common return for USB-C, battery connector negative, charger, buck, and 3.3 V bulk capacitors
- USB_CC1 and USB_CC2: J3 CC pins each terminated with 5.1 kΩ pull-downs
Current Charger Configuration
- U2 ~CE tied to GND so charging is enabled by default
- U2 EN1 and EN2 tied to GND, selecting USB100 mode at present
- R3 provides an ILIM programming resistor footprint for future resistor-programmed input current operation
- R4 programs approximately 0.8 A fast-charge current
- R5 provides valid TS bias with no thermistor-equipped battery pack required
Implemented Regulator Configuration
- IC1 VIN is fed from SYS
- IC1 EN is tied high to SYS so the buck is on whenever system power is available
- L1 is the 2.2 µH switching inductor
- C5 is the buck input capacitor and C6 is the buck output capacitor
- R6 connects from VSET to GND to set the 3.3 V output target
- C7 provides additional bulk support on the 3.3 V rail near the ESP32 domain
15W Payload Switch Implementation
- Q1 is CSD18532Q5B configured as a dedicated low-side payload switch
- J4 is the external 2-pin screw terminal for the switched payload output
- J4 Pin 1 is tied to +BAT_RAW so the external payload receives raw battery positive
- J4 Pin 2 is tied to the Q1 drain on net 15W_PAYLOAD, providing the switched low-side return path
- Q1 source pins and exposed pad are tied directly to GND
- U1 IO4 is assigned as the payload control GPIO on net PAYLOAD_CTRL
- R9 is the 100R series gate resistor between U1 IO4 and the Q1 gate
- R10 is the 10k pull-down from the Q1 gate to GND so the payload remains off during reset or high impedance states
- This low-side topology is suitable only when the payload can tolerate switched ground; if the future payload is inductive, add a flyback diode at the connector
Output Header Pinout And Expected Load Current Notes
- J1 programming header pinout: Pin 1 = UART0_TX0, Pin 2 = UART0_RX0, Pin 3 = ESP_EN, Pin 4 = ESP_BOOT
- J1 expected load current: logic and control only, not a power-output header
- J4 payload header pinout: Pin 1 = +BAT_RAW, Pin 2 = 15W_PAYLOAD switched low-side return
- J4 expected load current baseline: battery-path routing and rule constraints are sized for up to 5 A on the +BAT_RAW path
- J5 through J10 motor header pinout is recorded in the motor mapping section above for each bridge output pair
- J5 through J10 expected motor load current: TBD from final motor selection and detailed DRV8833 operating limits review
- ADHESION_1 pinout: Pin 1 = +BAT_RAW, Pin 2 = ADHESION_1_SW
- ADHESION_2 pinout: Pin 1 = +BAT_RAW, Pin 2 = ADHESION_2_SW
- ADHESION_3 pinout: Pin 1 = +BAT_RAW, Pin 2 = ADHESION_3_SW
- ADHESION_1, ADHESION_2, and ADHESION_3 expected load current: TBD from the final adhesion load definition; current budget is not yet assigned in this revision
Camera And Optical Flow Integration
- Reserved ESP32-S3 pins preserved and not reassigned: TXD0, RXD0, EN, IO0, IO4, IO1, IO2, IO3, IO5 through IO16
- OV2640 camera interface added through FPC1, a 24-pin 0.5 mm FPC connector
- SCCB control bus uses U1 IO17 = CAM_SIOD and U1 IO18 = CAM_SIOC with R14 and R15 as 4.7k pull-ups to 3V3
- OV2640 timing signals use U1 IO19 = CAM_XCLK, U1 IO20 = CAM_PCLK, U1 IO21 = CAM_VSYNC, and U1 IO47 = CAM_HREF
- OV2640 data bus mapping uses U1 IO48 = CAM_D0, IO45 = CAM_D1, IO46 = CAM_D2, IO35 = CAM_D3, IO36 = CAM_D4, IO37 = CAM_D5, IO38 = CAM_D6, IO39 = CAM_D7
- OV2640 control lines use U1 IO40 = CAM_RESETB and U1 IO41 = CAM_PWDN
- Dedicated optical-flow SPI bus uses U1 IO42 = FLOW_SPI_SCK with U3 SCLK, plus FLOW_SPI_MOSI, FLOW_SPI_MISO, and FLOW_SPI_CS wired only to U3 and reserved for the optical-flow subsystem
- Optical-flow auxiliary signals are FLOW_MOTION and FLOW_RESET
- Exact PMW3901 part was not available in the library, so U3 is a PixArt SPI optical-sensor placeholder used to complete reserved-bus integration and documentation
Motor Header Output Mapping
- J5 is the motor header for IC2 bridge A
- J5 P1 = DRIVER2_MOTOR_A_P connected to IC2 AOUT1
- J5 P2 = DRIVER2_MOTOR_A_N connected to IC2 AOUT2
- J6 is the motor header for IC2 bridge B
- J6 P1 = DRIVER2_MOTOR_B_P connected to IC2 BOUT1
- J6 P2 = DRIVER2_MOTOR_B_N connected to IC2 BOUT2
- J7 is the motor header for IC3 bridge A
- J7 P1 = DRIVER3_MOTOR_A_P connected to IC3 AOUT1
- J7 P2 = DRIVER3_MOTOR_A_N connected to IC3 AOUT2
- J8 is the motor header for IC3 bridge B
- J8 P1 = DRIVER3_MOTOR_B_P connected to IC3 BOUT1
- J8 P2 = DRIVER3_MOTOR_B_N connected to IC3 BOUT2
- J9 is the motor header for IC4 bridge A
- J9 P1 = DRIVER4_MOTOR_A_P connected to IC4 AOUT1
- J9 P2 = DRIVER4_MOTOR_A_N connected to IC4 AOUT2
- J10 is the motor header for IC4 bridge B
- J10 P1 = DRIVER4_MOTOR_B_P connected to IC4 BOUT1
- J10 P2 = DRIVER4_MOTOR_B_N connected to IC4 BOUT2
ESP32 PWM GPIO Assignment For Motor Drivers
- Reserved lines preserved: TXD0 on UART0_TX0, RXD0 on UART0_RX0, EN on ESP_EN, IO0 on ESP_BOOT, and IO4 on PAYLOAD_CTRL
- U1 IO5 -> IC2 AIN1 on net DRV2_AIN1_PWM
- U1 IO6 -> IC2 AIN2 on net DRV2_AIN2_PWM
- U1 IO7 -> IC2 BIN1 on net DRV2_BIN1_PWM
- U1 IO8 -> IC2 BIN2 on net DRV2_BIN2_PWM
- U1 IO9 -> IC3 AIN1 on net DRV3_AIN1_PWM
- U1 IO10 -> IC3 AIN2 on net DRV3_AIN2_PWM
- U1 IO11 -> IC3 BIN1 on net DRV3_BIN1_PWM
- U1 IO12 -> IC3 BIN2 on net DRV3_BIN2_PWM
- U1 IO13 -> IC4 AIN1 on net DRV4_AIN1_PWM
- U1 IO14 -> IC4 AIN2 on net DRV4_AIN2_PWM
- U1 IO15 -> IC4 BIN1 on net DRV4_BIN1_PWM
- U1 IO16 -> IC4 BIN2 on net DRV4_BIN2_PWM
Approved Module
Interface Compatibility Review
Required Electrical Interfaces
RF and Layout Requirements
Acceptance Criteria
Programming Header Baseline
Current Integration State
Implemented Signal Mapping
PCB Keep-Out Baseline
Power Architecture Decision
BQ24075 Implementation Notes
TPS62840 Implementation Notes
USB-C Power Input Notes
Implemented Power Components
Implemented Power Net Mapping
Current Charger Configuration
Implemented Regulator Configuration
15W Payload Switch Implementation
Output Header Pinout And Expected Load Current Notes
Camera And Optical Flow Integration
Motor Header Output Mapping
ESP32 PWM GPIO Assignment For Motor Drivers
