Schematic Design Specification
1. Core IC
- Hub controller: USB2514B, 4-port USB 2.0 hub
- Preferred package for new designs: 36-pin SQFN
2. Required Schematic Blocks
2.1 Hub Core Power
- Connect all VDD33 and VDDA33 pins to regulated 3.3 V
- Place 0.1 uF decoupling capacitors close to each power pin:
- VDDA33 pins: one 0.1 uF per pin
- VDD33 pins: one 0.1 uF per pin
- Add 1.0 uF shared bulk capacitance on the 3.3 V rail local to the hub
- Tie the exposed pad/ePad to ground with multiple vias
- Use one common solid ground plane; separate analog/digital ground planes are not recommended
2.2 Core Analog Support
- RBIAS pin: connect 12.0 kOhm, 1% resistor to ground, placed very close to the pin
- CRFILT pin: may connect up to 0.1 uF low-ESR capacitor to ground, or may be left unconnected
- PLLFILT pin: may connect up to 0.1 uF low-ESR capacitor to ground, or may be left unconnected
- TEST pin: treat as no-connect or tie to ground; do not route signals to it
- NC pins: no connect, no routing
2.3 Clock Circuit
- Use 24.000 MHz ±350 ppm crystal or external 24 MHz clock
- If using crystal:
- connect between XTALIN and XTALOUT
- size C1/C2 to the crystal load requirement
- keep crystal loop compact and isolated from USB traces
- If using external clock:
- drive XTALIN/CLKIN only
- leave XTALOUT unconnected
2.4 Reset Circuit
- RESET_N must be held low for at least 1 us after all supplies are within operating range
- Recommended power-up reset network from hardware checklist:
- 10 kOhm pull-up to 3.3 V
- 1 uF capacitor to ground
- Errata workaround for SMBus/DP power-up glitch:
- keep RESET_N low during POR using external control or RC network
- errata example values: 100 kOhm pull-up to 3.3 V and 220 nF capacitor to ground
- Preferred implementation for robust designs: reset supervisor or MCU-controlled reset with timing validation
2.5 Upstream USB Port
- Connect USBDP_UP and USBDM_UP directly to the upstream USB connector D+ and D-
- Connect VBUS_DET to upstream VBUS through a 2:1 divider; suggested values are 100 kOhm / 100 kOhm
- Upstream VBUS capacitance shall not exceed 10 uF total
- Tie connector ground to PCB ground with low impedance
- Connector shield: recommended RC network to PCB ground using 330 Ohm || 0.1 uF
2.6 Downstream USB Ports
- Connect each USBDP_DNx / USBDM_DNx pair directly to the downstream connector data pins
- For any unused downstream port, disable the port by pulling both D+ and D- strap functions high to 3.3 V, or disable by EEPROM/SMBus configuration
- Each exposed downstream port shall include:
- VBUS power switch / port power controller
- over-current fault reporting to OCS_Nx
- downstream VBUS bulk capacitance up to 150 uF max per Microchip reference circuit
2.7 Port Power Controller Interface
- PRTPWRx should drive a controller enable input that is active-high and compatible with 3.3 V logic
- OCS_Nx should receive an active-low, open-drain FAULT indication
- If controller polarity or voltage is incompatible, add external inversion or level adaptation
2.8 Strap / Configuration Pins
- Define CFG_SEL pins based on selected configuration mode:
- 00: default config, self-powered default, individual switching, individual OC sensing, straps enabled
- 01: SMBus configuration
- 10: default config override for bus-powered operation
- 11: I2C EEPROM configuration
- Non-removable ports shall be strapped or configured for permanently attached devices
- Battery charging enable straps shall be implemented only on ports whose power path supports the required current
- LED/shared strap pins shall follow the strap resistor guidance of 47 kOhm to 100 kOhm where applicable
2.9 Optional EEPROM / SMBus
- EEPROM interface requires external pull-ups on SDA and SCL to VDD33; 10 kOhm recommended
- EEPROM must be 256 x 8-bit organization
- Hub reads EEPROM only; it does not program EEPROM
- If SMBus is selected, EEPROM mode is not available on the shared pins
3. Schematic Review Gates
- Pinout matches package and datasheet
- All power pins decoupled per checklist
- All exposed ports have VBUS switching and OC reporting
- Reset strategy documented and consistent with errata workaround
- Unused ports explicitly disabled
- Configuration mode documented
- Battery charging ports explicitly identified and power-sized