Project Start
READ-ONLY. Do not change anything. Short answer only.
Analyse the ESP32 auto-reset circuit around Q2, Q3, R15, R16 and the CH340G (U4).
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List the net on Base, Emitter and Collector of Q2 and Q3, and both ends of R15 and R16.
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The CH340G DTR# and RTS# outputs are active-low and sit at 3.3 V (high) whenever no host asserts them: on battery with no USB, with USB plugged in but no serial port open, and after esptool finishes. For that idle state, state the resulting level on ESP_EN and ESP_BOOT and whether the ESP32 (U1) is held in reset.
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Compare with the Espressif ESP32-DevKitC reference circuit, where each transistor's emitter is tied to the other control line (Q for EN: base from RTS#, emitter to DTR#; Q for IO0: base from DTR#, emitter to RTS#) so that both lines idle-high does nothing. State whether this board's circuit matches it or differs, and if it differs, which pins would need to change.
Thought for 55 sec
flux
Table
| Component | Base pin 1 | Emitter pin 2 | Collector pin 3 |
|---|---|---|---|
| Q2 | Net 4, through R15 from DTR# | GND | ESP_BOOT |
| Q3 | Net 5, through R16 from RTS# | GND | ESP_EN |
Table
| Resistor | Pin 1 | Pin 2 |
|---|---|---|
| R15 — 10 kΩ | CH340_DTR_N (U4 pin 13) | Net 4 → Q2 base |
| R16 — 10 kΩ | CH340_RTS_N (U4 pin 14) | Net 5 → Q3 base |
With both outputs at 3.3 V as specified: both transistors turn on, pulling ESP_EN LOW and ESP_BOOT LOW; U1 is held in reset. This applies to each listed operating state if those outputs are actually high; active-low naming alone does not guarantee their startup/driver state.
This differs from the cross-coupled reference you describe. To match it, Q2 emitter pin 2 must change from GND to
CH340_RTS_N, and Q3 emitter pin 2 from GND to CH340_DTR_N; bases, resistors and collectors stay as listed. Both-high would then leave both transistors off and allow EN/BOOT to pull high.Read-only: nothing changed.
for this design, BT1 was not in the pick and place file, can you correct that?
Worked for 1 min 9 sec
flux
BT1 is now enabled for pick-and-place, and I regenerated the JLCPCB CPL file, available above. Only BT1’s export setting changed—no placement, footprint, routing or net changes.
