Set the copper keepout/minimum keepout to 0.25 mm across traces/pads/vias/fills/nets, which controls spacing to the GND pour. Quick DRC still reports 4 pre-existing/open airwire issues, but no copper-overlap warnings were returned from the checked categories.

I’ll apply relief-connect thermal relief to GND-connected pads on the top and bottom copper layers, then run a quick DRC check for copper/airwire issues.

Applied thermal relief to the targeted GND/DGND/VSS pads on the board: Relief connect, 4 spokes, 0.25 mm spoke width, 45° spoke angle. The follow-up check shows airwire errors on GND-related pads/fill stitching, so the pour may need repour/reroute cleanup next; I did not change placement or routing.

I’ll find every net whose name contains “GND”, merge those into the main GND net in the schematic, then run ERC/DRC connectivity checks to catch any remaining split grounds.

I checked the schematic netlist and there are no separate “GND” nets to merge: everything ground-related is already on the main ^GND net, including DGND-labeled pins. The remaining GND/DGND items are PCB airwires to ground pads/fill/stitch vias, so the next fix would be repouring/rerouting GND copper rather than changing schematic connectivity.