# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** fabracht - **Created:** 12/13/2024 - **Last Updated:** 12/14/2024 - **Visibility:** Public ## Key Components ### U1 — [LMP91000SD/NOPB](https://www.flux.ai/adrian95/lmp91000sdnopb~pu2.md) - Datasheet URL: https://www.ti.com/lit/ds/symlink/lmp91000.pdf - License: https://creativecommons.org/licenses/by/4.0/ - Manufacturer Name: Texas Instruments - Manufacturer Part Number: LMP91000SD/NOPB - Part Type: Integrated Circuit **Pins:** - AGND [pin 7] - C1 [pin 10] - C2 [pin 9] - CE [pin 14] - DAP [pin 15] - DGND [pin 1] - MENB [pin 2] - NC [pin 5] - RE [pin 13] - SCL [pin 3] - SDA [pin 4] - VDD [pin 6] - VOUT [pin 8] - VREF [pin 11] - WE [pin 12] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/fabracht/2-layer-jlcpcb-constraints~n1](https://www.flux.ai/fabracht/2-layer-jlcpcb-constraints~n1).* --- *Generated from [https://www.flux.ai/fabracht/2-layer-jlcpcb-constraints~n1](https://www.flux.ai/fabracht/2-layer-jlcpcb-constraints~n1)*