This is a compact, USB-C-powered dual-output DC/DC supply. It accepts nominal 5 V USB power and generates two regulated rails:
1.8 V
3.3 V
Both outputs are exposed through 2-pin headers and include test points and indicator LEDs. The electronics are placed on a 40 × 40 mm, 2-layer PCB, with mounting holes and a two-piece enclosure model.
Its intended role is a small bench supply, embedded power module, or development-board accessory for low-voltage digital electronics.
Functional architecture
Diagram
Core componentsTPS62402 dual buck converter
The central component is the Texas Instruments TPS62402DRCT, a dual synchronous step-down converter operating at approximately 2.25 MHz.
Using one dual-channel IC instead of two separate regulators:
Reduces component count and board area
Shares the input supply and control infrastructure
Provides better efficiency than linear regulators
Avoids the heat that two LDOs would dissipate when converting 5 V to 1.8 V and 3.3 V
The trade-off is a more layout-sensitive design. Switching-node geometry, grounding, capacitor placement, and feedback routing become critical.
Both enable inputs are connected directly to USB 5 V, so the two rails start automatically when input power appears.
USB-C input
A GCT USB4215-03-A receptacle provides the 5 V input. Its VBUS pins feed:
The regulator input
A 10 µF input capacitor
An input-present LED
A USB-input test point
The connector shields and ground contacts are tied to board ground.
This connector is being used for power only; USB data is not part of the intended functionality.
Power inductors
Each buck channel uses a 2.2 µH Coilcraft LPS3010-class inductor:
L1: 1.8 V channel
L2: 3.3 V channel
These inductors convert the regulator’s switched waveform into continuous output current. The 3 × 3 mm package is a compromise among current handling, DC resistance, height, and PCB area.
Input and output capacitors
The power stage uses:
C1: 10 µF, 25 V X5R input capacitor
C2: 22 µF, 10 V X5R capacitor on 1.8 V
C3: 22 µF, 10 V X5R capacitor on 3.3 V
The input capacitor supplies high-frequency switching current locally rather than drawing each current pulse through the USB cable. The output capacitors reduce ripple and help stabilize the regulator control loops.
The capacitors use relatively large 1206 packages. This improves usable capacitance under DC bias but consumes more board area than 0805 or 0603 alternatives.
Feedback and configuration networks
The resistor networks connected to FB1, DEF_1, and ADJ2 configure the output voltages and operating behavior.
The 3.3 V channel uses a divider around the adjustable input. The nominal divider ratio is consistent with generating approximately 3.3 V from the regulator’s internal reference.
The 1.8 V channel uses the device’s feedback and definition/configuration pins to select or set that rail.
The MODE/DATA pin has a 10 kΩ configuration path and a DNP option. This appears intended to select the regulator’s operating mode while preserving a population option for later tuning.
Connectors and test points
The board has three 2-pin, 2.54 mm headers:
1.8 V and ground
3.3 V and ground
A mode/configuration-related connection
Test pads expose:
USB 5 V
1.8 V
3.3 V
Ground
These make bring-up and troubleshooting much easier and allow rail ripple or startup behavior to be measured without probing fine-pitch IC pins.
Indicator LEDs
Three red LEDs indicate:
USB input present
1.8 V rail present
3.3 V rail present
Series resistors limit their current. The input and 3.3 V indicators are conventional. The 1.8 V LED has very little voltage headroom because a red LED’s forward voltage can approach or exceed 1.8 V. Its brightness will therefore vary significantly between parts and with temperature.
Physical implementation
The PCB is:
40 × 40 mm
2 copper layers
Primarily top-side assembled
Mechanically supported by four nominal M4 mounting holes
Accompanied by enclosure bottom and lid models
The regulator and its two power channels are grouped near the center. USB-C enters from the left, while output headers and test points are generally placed toward the right.
High-frequency switching regulators benefit from this compact arrangement because shorter current loops reduce:
Radiated EMI
Ground bounce
Switching-node ringing
Parasitic inductance
Output ripple
However, the present design review reports that the board is extremely dense. Some of this density calculation is distorted by a large Flux logo extending outside the board, but the top side is still crowded.
Important design choices and trade-offsSwitching regulators instead of LDOs
This is the most important architectural decision.
Advantages:
Much higher efficiency
Lower temperature rise
Better battery or USB power utilization
Both rails generated by one small IC
Costs:
More layout-sensitive
Requires inductors and larger capacitors
Generates switching noise and EMI
Harder to debug than linear regulation
High switching frequency
At 2.25 MHz, the regulator can use small 2.2 µH inductors and compact capacitors.
The trade-off is increased switching loss and stronger sensitivity to PCB parasitics. Layout quality matters more than it would at a lower frequency.
Two-layer PCB
A two-layer board keeps fabrication inexpensive and accessible. It is adequate for a small converter when the power stage is placed carefully and the bottom layer is kept as continuous a ground reference as possible.
A four-layer implementation could improve grounding, thermal spreading, and EMI, but would increase cost.
Permanently enabled outputs
Connecting both enable inputs to USB 5 V keeps operation simple: plug it in and both rails turn on.
This eliminates software and switches, but it also means:
No independent output control
No intentional power sequencing
No low-power standby state
Both rails always consume quiescent current
Current design-review concerns
The project is conceptually sound, but the present implementation is not yet production-ready.
USB-C configuration is incomplete
The USB-C CC1 and CC2 pins are currently floating. A USB-C power sink normally requires the appropriate pull-down resistors on both CC pins to advertise itself as a sink.
Without these resistors, compliant USB-C sources may not enable VBUS reliably. This is the most important schematic issue.
The unused D+ and D− pins are also reported as floating. That is acceptable for a power-only product, but they should be explicitly marked as intentionally unused or given ESD handling if exposed-system robustness is required.
Output capacitor placement
The design review reports that C2 and C3 are positioned beyond their respective inductors, rather than closing the output-current loops toward the regulator ground.
For a 2.25 MHz converter, this can increase:
Output ripple
EMI
Ground-loop area
Load-transient overshoot
Control-loop sensitivity
The output capacitors should be placed so that each inductor-to-capacitor-to-ground loop is as short and wide as practical.
Exposed-pad copper conflicts
The layout reports overlapping copper around the regulator’s exposed ground pad and thermal vias. Some overlap may be intentional, but the current objects are being interpreted as conflicting copper.
This should be resolved before manufacturing because it may indicate duplicated traces, incorrectly assigned copper, or via geometry that does not match the intended exposed-pad implementation.
Mechanical keepout violations
All four mounting holes currently overlap keepout regions. The large logo also extends beyond the PCB and intersects a keepout.
These are primarily layout-cleanup issues, but mounting-hole clearances must be corrected to prevent hardware, washers, or standoffs from contacting nearby copper or components.
Unnecessary or redundant traces
Nine redundant-copper warnings are present. These appear to be dangling stubs, loops, or floating copper left by earlier routing iterations. They should be removed because they can:
Act as antennas
Create confusing manufacturing data
Reduce clearance
Obscure real routing problems
LED behavior on 1.8 V
A standard red LED is marginal when powered from 1.8 V. Production variation could make it dim or completely off even when the rail is correct.
Better options include:
A low-forward-voltage LED qualified at low current
A transistor-driven indicator
Omitting the 1.8 V LED
Using a voltage supervisor with an open-drain indicator output
Performance considerations
Actual performance will depend heavily on layout and component characteristics.
Key factors include:
Inductor saturation current and DC resistance
Ceramic-capacitor derating under DC bias
USB cable and source voltage drop
Thermal resistance of the VSON exposed pad
Load-current balance between outputs
Switching-node area
Feedback trace noise coupling
Ground-plane continuity
The LEDs also create continuous parasitic loads. This is minor for a USB bench supply but relevant for battery-operated applications.
The TPS62402’s thermal pad must be well connected to ground with appropriate copper and vias. At heavier simultaneous loads, enclosure airflow and copper area can become limiting even when the regulator is electrically within specification.
Real-world applications
This board is suitable as a starting point for:
FPGA or CPLD auxiliary power
Sensor and radio module supplies
Mixed-voltage microcontroller development
1.8 V logic-level experiments
Breadboard power distribution
Portable prototyping equipment
Embedded products requiring both 1.8 V and 3.3 V from USB
Production-test fixtures
It is particularly useful where both rails are required simultaneously and an external USB power bank or wall adapter is convenient.
Recommended improvements
Priority improvements are:
Add correct USB-C CC pull-down resistors.
Reposition C1, C2, C3, L1, and L2 to minimize high-current loop area.
Resolve the exposed-pad and thermal-via copper conflicts.
Correct mounting-hole keepouts and remove or resize the off-board logo.
Explicitly mark unused USB data and SBU pins as intentionally unconnected.
Remove redundant copper and rerun ERC/DRC.
Confirm inductor current rating and capacitor effective capacitance against maximum load.
Reconsider the 1.8 V indicator circuit.
Add USB input protection, such as ESD suppression and optionally a fuse or load switch.
Validate startup, ripple, efficiency, and thermal behavior under simultaneous maximum loading.
Future enhancements
Possible extensions include:
Independent enable controls for each rail
Output sequencing
Power-good indicators
Selectable or programmable output voltages
Output current limiting or electronic fuses
USB-C Power Delivery support for higher input voltage or power
Reverse-current and input-overvoltage protection
Current and voltage monitoring
Four-layer PCB for improved EMI and thermal behavior
Castellated edges or smaller connectors for module integration
Improved enclosure access to test points and headers
Overall, the project uses a strong compact architecture: one high-frequency dual buck IC generates two commonly required digital rails from USB-C. Its primary remaining risks are USB-C sink configuration and high-frequency power-stage layout rather than the fundamental converter topology.
Re-annotated BOM/mechanical schematic components while preserving existing connectivity, values, footprints/packages, MPNs, and component properties. Net portals, power portals, and ground symbols were treated as schematic connectivity labels rather than BOM components and were not re-numbered.
Re-annotation scheme
Resistors: R1...R11, ordered left-to-right by schematic placement.
Capacitors: C1...C4, ordered left-to-right by schematic placement.
Connectors: USB connector first as J1, 2-pin header as J2.
Switches/sensors: SW1...SW2 using the existing SW prefix metadata.
ICs, transistors, diodes, LEDs, buzzer, and mounting holes were already in unique standard prefix groups and were retained unless noted.
Temporary labels TMP_* were used during the operation only to avoid duplicate designator conflicts.
The following named nets were verified after the re-annotation. Connectivity is functionally identical to the pre-change snapshot with only designator names updated.
Duplicate-reference ERC check passed after re-annotation.
Values, package/footprint properties, MPNs, manufacturer names, datasheet URLs, and custom notes were preserved because only designators were changed.
Existing design issues remain and were not introduced by re-annotation: floating pins on U3:CV, J1:ID, SW2:3, U2:DIS; single-pin USB_D_PLUS and USB_D_MINUS nets; and an existing missing-power warning for U1:VBAT on CHR_OUT.
Net portals, power portals, and ground symbols retain their label-style designators because renaming them would alter the readability/intent of named nets rather than re-annotating BOM components.