Project Overview


Project overview
This project is a low-noise analog guitar distortion pedal with digitally controlled true bypass. It accepts a guitar-level input, applies adjustable gain and symmetrical diode clipping, shapes the result with a tone control, sets output volume, and routes either the processed or bypassed signal to the output jack.
The design combines:
  • A largely analog audio path
  • Low-noise OPA1656 op-amps
  • Three panel controls: gain, tone, and volume
  • Relay-based true bypass
  • An ATtiny212 for footswitch and relay control
  • Anti-pop muting using a PhotoMOS switch
  • Protected 9 V input and a separate regulated 5 V control rail
  • A 100 × 60 mm, four-layer PCB and modeled pedal enclosure
Functional architecture

Diagram


Effect mode "9 V DC input" "Reverse-polarity protection and filtering" "Clean 9 V analog rail" "5 V LDO" "ATtiny212 control system" "Guitar input jack" "DPDT true-bypass relay" "Input buffer" "Variable-gain amplifier" "Symmetrical diode clipping" "Active tone stage" "Output volume control" "Output jack" "Relay transistor driver" "PhotoMOS anti-pop mute" "Status LED" "Soft-touch footswitch"
1. Power system
The pedal is powered through J1, a conventional barrel connector. Its nominal input is 9 V DC.
Protection and filtering
The input passes through:
  • Q1, AO3401A P-channel MOSFET — reverse-polarity protection with much lower voltage loss than a conventional series diode.
  • R1, 22 Ω — supply isolation and filtering.
  • Bulk and ceramic capacitors such as C23, C2, C3, C4, C5, C7, and C9.
  • Separate named rails including +9V_RAW, +9V_PROT, and +9V_CLEAN.
The OPA1656 analog circuitry runs from the cleaned 9 V rail. Because the circuit uses a single positive supply, it creates a mid-supply reference, or virtual ground, for the audio stages.
Control supply
U1, TPS70950, converts the protected input to 5 V. This rail powers:
  • The ATtiny212
  • The 5 V relay coil
  • Control-side switching circuitry
  • Status indication
Separating the analog supply from the regulated control rail helps prevent relay and microcontroller activity from coupling into the guitar signal.
Power trade-offs
The linear regulator is quiet and uncomplicated, but it dissipates the voltage difference as heat. That is acceptable here because the digital and relay-control loads are relatively small. A switching regulator would be more efficient, but could introduce switching noise into a high-gain audio circuit.
2. Audio signal path Input and bypass routing
CN2 is the guitar input and CN1 is the output. Both are Neutrik NMJ6HCD2 audio jacks.
The signal first encounters K1, an Omron G6S-2F 5 V DPDT relay. Its two poles switch both ends of the effect path:
  • In bypass, the input is connected directly to the output.
  • In effect mode, the input is sent into the processing chain and the processed output is returned to the output jack.
This is genuine electromechanical true bypass rather than a permanently buffered bypass.
High-value 1 MΩ resistors provide input and output bias paths and help discharge coupling capacitors. This reduces clicks when the relay changes state.
Input buffer
One amplifier section of U5, an OPA1656 dual op-amp, forms the input buffer. The OPA1656 is a good fit because it offers:
  • JFET inputs and very high input impedance
  • Low voltage and current noise
  • Low distortion
  • Rail-to-rail output behavior suitable for single-supply audio
  • Enough bandwidth for high closed-loop gain without compromising the guitar band
The buffer isolates the guitar pickups from the variable-gain and clipping networks. This prevents the pedal’s controls from excessively loading the instrument and preserves high-frequency response.
Gain and distortion stage
An amplifier section of U6 provides the main adjustable gain. VR1 is the gain control, working with the surrounding feedback resistors and capacitors.
D3 and D4, both 1N4148-family switching diodes, are connected in opposite directions in the feedback or clipping path. They create approximately symmetrical clipping:
  • Small signals are amplified approximately linearly.
  • As the signal amplitude rises, one diode conducts on each polarity.
  • The amplifier’s effective feedback changes, compressing and clipping both halves of the waveform.
Symmetrical silicon clipping produces a relatively tight, focused distortion with predominantly odd-order harmonic content. It is generally more aggressive and less “asymmetric” than LED, germanium, or intentionally mismatched clipping.
Small capacitors around this stage constrain high-frequency gain. This improves stability and avoids amplifying noise far beyond the audible range.
Tone control
VR2 and another OPA1656 section form the active tone-shaping stage. The associated resistor-capacitor network blends or emphasizes different portions of the distorted spectrum.
This stage is important because clipping generates substantial high-frequency harmonic content. Without filtering, the result can sound harsh or fizzy. The active topology also avoids the large insertion loss found in many passive guitar-pedal tone stacks.
Output level
VR3 is the output-volume control. A coupling capacitor blocks the internal DC bias while passing the audio signal to the potentiometer and output switching network.
This lets the user compensate for the gain introduced by the distortion circuit and set unity gain or a boosted output level.
3. Bypass and anti-pop control Microcontroller
U2, ATtiny212, monitors the momentary footswitch S1 and controls the pedal state.
The controller is responsible for:
  • Switch debouncing
  • Toggling effect/bypass state
  • Driving the status LED
  • Sequencing the mute and relay
  • Providing deterministic startup behavior
A three-pin header, H1, exposes power, ground, and PA0/UPDI for programming.
Relay driver
The microcontroller cannot safely drive the relay coil directly. Q2, BC817-40, acts as a low-side relay driver. A base resistor limits MCU output current, while a pull-down keeps the transistor off during reset.
D2 is the relay flyback diode. It clamps the coil’s inductive voltage when Q2 turns off, protecting both the transistor and microcontroller.
Anti-pop mute
U3, AQY212GSZ PhotoMOS relay, provides a temporary signal mute during switching.
A likely control sequence is:
  1. Activate the mute.
  2. Change the mechanical relay state.
  3. Wait for contacts and bias voltages to settle.
  4. Release the mute.
This addresses the main weakness of relay bypass: audible pops caused by contact switching, stored capacitor charge, or small DC differences between signal nodes.
The PhotoMOS solution gives galvanic isolation and avoids putting a conventional transistor’s nonlinear junction directly in the signal path. Its disadvantages are higher cost and nonzero on-resistance and capacitance.
4. Mechanical and PCB implementation
The PCB is:
  • 100 × 60 mm
  • Rectangular with 3 mm corner radii
  • Four copper layers
  • Populated primarily on the top side
  • Equipped with four M2 mounting holes
  • Integrated with a modeled enclosure, top panel, knobs, and internal fasteners
The input and output jacks sit along one side of the board, while the three potentiometers align with the enclosure’s control openings. The footswitch, LED, power jack, and programming header are also board-mounted.
The board is dense:
  • 73 physical components
  • Approximately 65.8% top-side component-area fill
  • Approximately 97.6% routing-aware occupancy
A four-layer stackup is therefore a practical choice. Internal planes reduce routing congestion and provide low-impedance ground and power distribution.
Important design choices OPA1656 instead of a commodity pedal op-amp
The OPA1656 improves input impedance, noise, distortion, and output drive compared with older devices commonly found in pedals.
The trade-off is price. In a deliberately lo-fi distortion circuit, the audible improvement may be smaller than the component cost suggests, but it helps keep noise and unintended coloration below the intentional distortion.
Relay bypass instead of electronic bypass
Benefits:
  • True galvanic signal routing
  • Very low signal resistance
  • Familiar true-bypass behavior
  • No semiconductor permanently in the bypass signal path
Costs:
  • Mechanical wear
  • Coil current
  • Larger footprint
  • Audible clicking
  • Need for flyback protection and anti-pop sequencing
Digital control around an analog signal path
The MCU improves switch behavior without digitizing the audio. This preserves the immediacy and simplicity of analog distortion while enabling debouncing, state control, muting, and future firmware features.
The main risk is digital noise coupling into the audio circuitry. Supply separation, local decoupling, ground management, and careful layout are essential.
Single-supply operation
Running the op-amps from 9 V and biasing the signal around a virtual reference avoids the cost and complexity of generating a negative rail.
The trade-offs are:
  • Reduced headroom compared with a bipolar supply
  • Dependence on a clean, low-impedance reference
  • Coupling capacitors at signal boundaries
  • Potential startup or switching transients while bias points settle
Performance considerations Noise
The dominant noise sources are likely to be:
  • High-value 1 MΩ bias resistors
  • Large gain settings
  • Guitar pickup and cable noise
  • Power-supply contamination
  • PCB coupling between the MCU, relay coil, and analog stages
The OPA1656 helps, but total noise will still rise substantially at maximum gain. Keeping high-impedance nodes short and clean is particularly important.
Headroom and clipping
The 9 V supply gives reasonable pedal-level headroom, but the internal audio signal is centered around a virtual reference. The available swing is therefore less than the full supply voltage.
At high gain, clipping may occur at both the intended diodes and the op-amp output limits. Whether that sounds desirable depends on the exact gain range and bias stability.
Frequency response
The small capacitors in the gain and feedback networks appear intended to:
  • Limit ultrasonic gain
  • Reduce hiss
  • Smooth diode-generated harmonics
  • Maintain op-amp stability
Excessive filtering could make the pedal sound dull, while insufficient filtering could produce harshness or RF sensitivity.
Switching performance
The relay and PhotoMOS sequence depends on firmware timing. If the mute interval is too short, pops may remain. If it is too long, the player will perceive a dropout or delayed response.
A good implementation should also reject switch bounce and prevent rapid repeated relay actuation.
Potential challenges
  • Grounding: High-gain analog circuitry shares the board with relay and MCU current pulses.
  • Virtual-reference integrity: Noise or loading on the reference affects every audio stage.
  • Dense layout: The board is tightly packed despite using four layers.
  • Mechanical alignment: Board-mounted jacks, pots, LED, switch, and enclosure holes must all align accurately.
  • Potentiometer availability: The selected Alps parts are mechanically specific and may constrain sourcing.
  • Relay lifetime: Mechanical relays have a finite switching life, although guitar-signal currents are very low.
  • Pop suppression: Component leakage, relay timing, or DC offsets can still create switching artifacts.
  • Thermal and power behavior: The relay is likely the largest 5 V load and must remain within the LDO’s current and dissipation limits.
  • Firmware dependency: A control-firmware fault can leave the pedal muted, in the wrong state, or repeatedly switching.
Real-world applications
The design is suitable for:
  • Stage and studio guitar rigs
  • Boutique analog effects products
  • A platform for comparing clipping networks
  • An educational example of mixed-signal audio design
  • A base architecture for overdrive, fuzz, boost, or preamp products
It could also be adapted for bass by changing coupling and tone-network corner frequencies.
Recommended improvements
  1. Validate the analog path with simulation and measurement. Confirm gain range, clipping thresholds, tone-control response, output level, and op-amp headroom.
  2. Characterize the virtual reference. Check its impedance and transient response at maximum signal level.
  3. Verify the 5 V power budget. Include relay pickup current, LED current, PhotoMOS drive, MCU consumption, and TPS709 thermal dissipation.
  4. Add accessible test points for 9 V raw, 9 V protected, 9 V clean, 5 V, virtual reference, effect input, drive output, and effect output.
  5. Review protection at external connectors. The audio jacks currently do not appear to have dedicated ESD or RF-input protection.
  6. Optimize sourcing. Several parts are extended or mechanically specialized; production variants should use stable, second-sourceable parts where possible.
  7. Improve diagnostic firmware. Add power-on self-test, relay-state indication, watchdog recovery, and a controlled default state.
  8. Consider clipping options. A switch or jumper could select silicon, LED, asymmetric, MOSFET, or no-diode clipping.
  9. Consider buffered bypass as an alternate mode. This could preserve treble in long cable runs, although it would no longer be strict true bypass.
  10. Run complete ERC, DRC, audio simulation, and physical fit verification before manufacturing, especially given the board density and enclosure integration.

Relay Distortion Path Debug Analysis
Executive summary
The relay coil/driver and flyback diode orientation in the schematic are logically correct now: D2 cathode is on +5V, D2 anode is on RELAY_COIL_NEG, Q2 collector is on RELAY_COIL_NEG, and Q2 emitter is on ground.
The most important schematic issue I found is the relay contact mapping: the Flux symbol for K2 labels COM1 as pin 3 and NC1 as pin 4, but the Omron G6S-2F datasheet pinout shows COM pins are 4 and 9, NC pins are 3 and 10, and NO pins are 5 and 8 for the SMD G6S-2F top view. That means the schematic symbol/footprint pin-function mapping is likely wrong or mirrored for at least the COM/NC contacts. This can absolutely produce the symptom: relay clicks, but the effect path is not actually routed where the schematic appears to say it is.
A second likely issue is the anti-pop photorelay U4: it is wired from EFFECT_OUT to GND, so if PA6 drives U4 on during normal effect operation, it will short/mute the effect output.
1. Relay K2 routing truth table
Datasheet pin mapping for Omron G6S-2F
For Omron G6S-2F-DC5 / G6S-2F-Y-DC5, the contact pinout found from the Omron datasheet/web result is:

Table


Relay functionPhysical pins
Coil1 and 12
COM4 and 9
NC3 and 10
NO5 and 8
Important: Omron shows the G6S-2F SMD terminal arrangement as top view. The through-hole version uses a bottom-view drawing. If a footprint/symbol was created from the wrong view, the contact functions can be mirrored/swapped.
K2 symbol pin mapping currently in Flux schematic
The K2 schematic symbol currently exposes these pins:

Table


Flux K2 pin namePin number in symbol
1 +1
12 -12
COM13
NCl14
NO15
NO28
NCl29
COM210
This conflicts with the Omron datasheet mapping above:
  • Flux says COM1 = 3, but datasheet says pin 3 is NC.
  • Flux says NCl1 = 4, but datasheet says pin 4 is COM.
  • Flux says NCl2 = 9, but datasheet says pin 9 is COM.
  • Flux says COM2 = 10, but datasheet says pin 10 is NC.
  • NO pins 5 and 8 appear correct.
Intended logical routing from the schematic labels
Based on the schematic labels and adjacent bias resistors, the intended audio relay routing appears to be:

Table


Logical netEvidence in schematic
JACK_IN_TIPtied to K2 pole 1 common side with R6 1M pulldown
EFFECT_INtied to K2 pole 1 NO side, R11 input resistor, R7 1M pulldown
BYPASS_LINKtied to both NC contacts
EFFECT_OUTtied to K2 pole 2 NO side, R21 series/output path, U4 mute, R8 1M pulldown
JACK_OUT_TIPtied to K2 pole 2 common side
If the relay symbol were correct, the desired truth table would be:

Table


Relay statePole 1 connectionPole 2 connectionResult
OFF / de-energizedJACK_IN_TIP → BYPASS_LINKJACK_OUT_TIP → BYPASS_LINKBypass path active
ON / energizedJACK_IN_TIP → EFFECT_INJACK_OUT_TIP → EFFECT_OUTDistortion path active
Actual physical behavior if the footprint follows the Omron datasheet
Because the schematic symbol appears to assign COM/NC incorrectly, the physical relay may behave differently from the schematic view.
Using the Omron physical mapping:
  • Pin 3 is actually NC, not COM.
  • Pin 4 is actually COM, not NC.
  • Pin 9 is actually COM, not NC.
  • Pin 10 is actually NC, not COM.
That means a board built from this footprint could have the physical commons on the nets intended to be NC/bypass, while the nets intended to be commons are actually NC terminals. The NO contacts may still go to the effect input/output, but the relay common may not be on JACK_IN_TIP / JACK_OUT_TIP. This is the top suspect for “relay clicks but no effect signal.”
Answer to the requested relay questions
  • Relay OFF expected: JACK_IN_TIP connects to BYPASS_LINK; JACK_OUT_TIP connects to BYPASS_LINK.
  • Relay ON expected: JACK_IN_TIP connects to EFFECT_IN; EFFECT_OUT connects to JACK_OUT_TIP.
  • Is COM/NC/NO mapping correct? The current Flux K2 symbol mapping does not match the Omron G6S-2F pinout found from the datasheet/web result. NO pins look correct; COM/NC pins appear swapped.
  • Could the footprint be mirrored or using bottom-view numbering incorrectly? Yes. The G6S-2F SMD datasheet diagram is top view; using a bottom-view interpretation can mirror/swap contact functions. Also, the symbol itself already appears inconsistent with the datasheet pin functions.
2. D2 flyback diode orientation
Schematic connections:
  • D2 cathode K → +5V
  • D2 anode A → RELAY_COIL_NEG
  • K2 coil positive pin 1 → +5V
  • K2 coil negative pin 12 → RELAY_COIL_NEG
  • Q2 collector → RELAY_COIL_NEG
This is the correct flyback orientation for a low-side relay driver.
Correct installed orientation:
  • D2 stripe/cathode side: +5V / relay coil positive
  • D2 anode side: RELAY_COIL_NEG / Q2 collector / relay coil negative
If D2 is reversed, it becomes forward-biased whenever Q2 turns on, effectively shorting +5V through D2 and Q2 to ground. Symptoms can include regulator collapse, high current, Q2 overheating, diode damage, or the relay not energizing properly. Temporarily removing D2 allows the relay to click, but it removes inductive kick protection and can stress Q2/U2 over time.
3. Q2 relay driver verification
Schematic connections match the expected low-side NPN driver:
  • U2 PA1 → R4 4.7k → Q2 base
  • R5 100k pulls Q2 base to GND
  • Q2 emitter → GND / DGND
  • Q2 collector → RELAY_COIL_NEG
  • Relay coil positive → +5V
Expected voltages when relay is ON:

Table


NodeExpected voltage
U2 PA1about 5 V
Q2 baseabout 0.6–0.8 V
Q2 emitter0 V
Q2 collector / RELAY_COIL_NEGabout 0–0.3/0.6 V
Across relay coilabout 4.5–5 V
This part of the schematic is consistent with the relay clicking.
4. U4 photorelay / mute analysis
U4 is a Toshiba TLP3431 photorelay. In this schematic it is wired as an output mute:
  • U4 input LED anode A is driven from PA6 through R3 1.2k.
  • U4 input cathode C goes to GND.
  • U4 output terminals are between EFFECT_OUT and GND.
Therefore:
  • PA6 HIGH → current flows through R3 and U4 input LED → photorelay output turns ON → EFFECT_OUT is shorted/muted to GND.
  • PA6 LOW → U4 input LED off → photorelay output open → EFFECT_OUT is not muted.
Answers:
  • Is U4 intended as anti-pop mute? Yes, based on its placement from EFFECT_OUT to ground.
  • Should U4 be ON only briefly during relay switching? Yes. It should normally be ON only around the switching transient, then released.
  • Should U4 be OFF during normal effect ON operation? Yes. During normal audio operation, U4 must be OFF or it can mute the output.
  • If PA6 keeps U4 ON, could it completely mute the distortion output? Yes. It directly shunts EFFECT_OUT to GND.
  • What should PA6 logic be?
    • Bypass steady state: normally LOW unless you intentionally mute during switching.
    • Switching interval: HIGH briefly to mute EFFECT_OUT during relay transition.
    • Effect ON steady state: LOW.
A quick test is to force PA6 LOW or temporarily disconnect U4/R3 and check whether the effect path returns.
5. VREF and analog power verification
Analog power
The op-amp supply net appears correct:
  • +9V_CLEAN corresponds to the schematic net containing U5 V+, U6 V+, C3/C8/C9/C10/C11 decoupling, and R9 top of VREF divider.
  • U5 V- and U6 V- are connected to GND.
Expected measurement:
  • U5 pin 8 / U6 pin 8 to GND: about +9 V, depending on adapter/battery and protection drop.
  • U5 pin 4 / U6 pin 4 to GND: 0 V.
VREF generation
VREF is generated by R9/R10:
  • R9 47k from +9V_CLEAN to VREF
  • R10 47k from VREF to GND
Expected VREF:
  • VREF ≈ +9V_CLEAN / 2
  • With 9.0 V clean supply: about 4.5 V.
  • With diode/MOSFET/protection losses and battery variation: roughly 4–4.5 V is normal.
VREF has decoupling/filtering around the analog section; if VREF is missing or near 0 V/9 V, the op-amps will bias incorrectly and the effect path can be silent or badly distorted.
Grounding
The schematic uses portals named DGND, but the actual power portal appears to tie into the global GND net. Analog and digital grounds appear connected as one net, which is acceptable for this single-supply pedal if layout return currents are handled carefully.
6. Distortion signal path review
The intended signal flow appears to be:
  1. JACK_IN_TIP
  2. Relay K2 pole 1, energized state
  3. EFFECT_IN
  4. R11/C14 into U5 buffer/input network
  5. BUFFER_OUT
  6. Gain/clipping stage around U6A with D3/D4
  7. DRIVE_OUT
  8. Tone network / tone pot terminals
  9. Volume/output network / volume pot terminals
  10. EFFECT_OUT
  11. Relay K2 pole 2, energized state
  12. JACK_OUT_TIP
Potential schematic problems found:
  • Relay COM/NC pin mapping is likely wrong relative to Omron’s actual G6S-2F pinout. This is the main suspect.
  • U4 can mute EFFECT_OUT if PA6 is HIGH during normal effect operation.
  • ERC reports Net 31 is a single-pin net at R21:P2. Because R21 appears to be the output series resistor from EFFECT_OUT, a single-pin net on R21:P2 is suspicious. It may mean the final output side of the volume/effect output path is not actually connected to where intended.
  • ERC reports Net 32 is a single-pin net at C20:2. This may be part of the output coupling/volume network; if one side of a coupling capacitor is left floating, the signal path can be open.
  • ERC reports floating GAIN_FB portals. This may be a portal/label artifact, but gain-stage feedback should be checked carefully.
7. Potentiometer checks
The potentiometers are represented as separate terminal components, so the schematic relies on correct external wiring/pin numbering. Verify the physical pot wiring against the intended nets:
  • Gain pot: terminals associated with gain feedback/inverting node must form a feedback/control path, not leave the op-amp feedback open.
  • Tone pot: wiper must connect to TONE_WIPER; tone network endpoints should not short signal permanently to ground unless at an extreme setting.
  • Volume pot: the output/wiper must actually reach EFFECT_OUT through the intended coupling/series resistor path.
The single-pin ERC warnings at R21:P2 and C20:2 strongly suggest checking the volume/output section first.
8. Clipping diodes D3/D4
D3 and D4 are connected anti-parallel between the gain-stage nodes:
  • One side group: D3:1, D4:2, R14:P2, C16:2, C17:1, U6:OUTA
  • Other side group: D3:2, D4:1, R13:P2, C16:1, U6:-INA
That is consistent with symmetrical clipping in the op-amp feedback/gain stage. They do not appear to be accidentally shorting directly to ground. They are unlikely to be the primary cause of total silence unless one diode is physically shorted or the surrounding gain feedback path is open.
9. Measurement checklist
Perform these with the pedal on the bench, using circuit ground as the black probe reference unless stated otherwise.
Power off / continuity checks
  1. Relay contact truth table at K2 pins directly
    • Relay OFF:
      • Pin 3 ↔ pin 4 or pin 4 ↔ pin 3? Determine which physical pins are closed.
      • Pin 9 ↔ pin 10 or pin 10 ↔ pin 9? Determine which physical pins are closed.
    • Relay ON:
      • Pin 4 ↔ pin 5 should close if Omron datasheet mapping is correct.
      • Pin 9 ↔ pin 8 should close if Omron datasheet mapping is correct.
  2. Expected bypass continuity, relay OFF
    • JACK_IN_TIP ↔ BYPASS_LINK: should be near 0 Ω.
    • JACK_OUT_TIP ↔ BYPASS_LINK: should be near 0 Ω.
    • JACK_IN_TIP ↔ EFFECT_IN: should be open.
    • JACK_OUT_TIP ↔ EFFECT_OUT: should be open.
  3. Expected effect continuity, relay ON
    • JACK_IN_TIP ↔ EFFECT_IN: should be near 0 Ω.
    • JACK_OUT_TIP ↔ EFFECT_OUT: should be near 0 Ω, possibly through R21 depending where you probe.
    • BYPASS_LINK should be disconnected from the active audio path.
  4. D2 diode orientation
    • Stripe/cathode pad continuity to +5V.
    • Non-stripe/anode pad continuity to RELAY_COIL_NEG / Q2 collector / K2 pin 12.
  5. EFFECT_OUT to GND resistance, power off
    • With U4 off/unpowered, EFFECT_OUT should not be a hard short to ground.
    • If it reads near 0 Ω, suspect U4 stuck on/shorted, solder bridge, or wrong net connection.
  6. Check R21 and C20 suspicious open nodes
    • R21:P2 should connect to the intended next node/output path, not be isolated.
    • C20:2 should connect to the intended output/volume network, not be isolated.
Power on / DC voltage checks
  1. +9V_CLEAN to GND
    • Expect roughly the adapter/battery voltage after protection, typically near 9 V.
  2. +5V to GND
    • Expect about 5.0 V.
  3. VREF to GND
    • Expect about half of +9V_CLEAN, typically 4–4.5 V.
  4. Op-amp supplies
  • U5/U6 V+ to GND: +9V_CLEAN.
  • U5/U6 V- to GND: 0 V.
  1. Relay driver ON state
  • PA1: about 5 V.
  • Q2 base: about 0.6–0.8 V.
  • Q2 collector / RELAY_COIL_NEG: about 0–0.6 V.
  • K2 coil pin 1 to pin 12: about 4.5–5 V.
  1. U4 mute / PA6
  • During normal effect ON steady state, PA6 should be LOW.
  • If PA6 is HIGH, U4 is probably muting EFFECT_OUT.
  • Measure EFFECT_OUT DC: it should usually sit around VREF through biasing/output network, not hard 0 V, unless AC-coupled after the final cap.
Audio probe checks
  1. Inject a small guitar/sine signal and probe in order:
  • EFFECT_IN
  • U5 buffer output / BUFFER_OUT
  • U6 gain-stage output / DRIVE_OUT
  • tone output / TONE_WIPER
  • volume output / EFFECT_OUT
  • JACK_OUT_TIP with relay ON
The first point where signal disappears identifies the failing block.
10. Likely fault list
Most likely causes, in priority order:
  1. K2 symbol/footprint COM/NC mapping mismatch with the Omron G6S-2F datasheet. This is the strongest schematic-level suspect.
  2. Relay footprint mirrored or interpreted from the wrong view. G6S-2F SMD drawing is top view; bottom-view interpretation can swap physical connectivity.
  3. U4 photorelay mute held ON by PA6, shorting EFFECT_OUT to ground during normal effect mode.
  4. Output path open near R21 or C20, supported by ERC single-pin-net warnings on R21:P2 and C20:2.
  5. Volume pot wiring/wiper not connected to EFFECT_OUT, especially because the pot terminals are generic terminals and depend on physical harness/pin numbering.
  6. VREF missing or wrong, which would bias the op-amps incorrectly.
  7. +9V_CLEAN missing at U5/U6, leaving the analog stages unpowered.
  8. Gain feedback path open or mislabeled, suggested by floating GAIN_FB ERC warnings.
  9. D2 reinstalled reversed, which would short the relay supply when Q2 turns on; however, with D2 removed and K2 clicking, this is not the current cause of no distortion sound.
  10. Physical solder/assembly issue on K2, U4, pots, or output coupling components.
Before changing firmware, verify K2 physical relay contact continuity with a meter directly at the relay pins. If the physical relay follows the Omron pinout, update/fix the K2 part symbol/footprint mapping so pins 4 and 9 are COM, pins 3 and 10 are NC, and pins 5 and 8 are NO. Also force PA6 LOW during steady-state effect ON or temporarily disable U4 to confirm it is not muting EFFECT_OUT.

  • Executive summary

  • 1. Relay K2 routing truth table

  • Datasheet pin mapping for Omron G6S-2F

  • K2 symbol pin mapping currently in Flux schematic

  • Intended logical routing from the schematic labels

  • Actual physical behavior if the footprint follows the Omron datasheet

  • Answer to the requested relay questions

  • 2. D2 flyback diode orientation

  • 3. Q2 relay driver verification

  • 4. U4 photorelay / mute analysis

  • 5. VREF and analog power verification

  • Analog power

  • VREF generation

  • Grounding

  • 6. Distortion signal path review

  • 7. Potentiometer checks

  • 8. Clipping diodes D3/D4

  • 9. Measurement checklist

  • Power off / continuity checks

  • Power on / DC voltage checks

  • Audio probe checks

  • 10. Likely fault list

  • Recommended next action