Regenerative Braking Design Discussion
Worked for 3 mins 17 sec
The generator inputs, bridge rectifiers, TVS clamp, supercapacitor equivalent, bleeder, and protected bus are wired; I’m wiring the charger, battery, and load rails next.
Worked for 10 mins 21 sec
Created the full schematic for the regenerative braking charger and renamed the project to Regenerative Braking Charger. I added/wired the motor inputs, dual bridge rectifiers, TVS clamp, supercapacitor equivalent, BQ25750 charger stage with external MOSFETs, 2S battery connector/protection, 5 V rail, 3.3 V RC522 rail, LCD/MCU/RFID connectors, and support passives.
Open items:
- BQ25750 bootstrap/compensation/feedback values still need datasheet-final tuning before layout.
- Supercapacitor bank is represented as an equivalent C1; final cell count, balancing, fuse, ESR, and discharge timing need sizing.
- I2C is pulled to 3.3 V for IC safety; add level shifting if your LCD module forces 5 V I2C pull-ups.
Suggested next steps:
- Finalize BQ25750 component values from the TI datasheet.
- Size the supercapacitor bank from expected braking energy.
- Move to PCB layout/placement after those values are locked.
- Use the new Board Bring-Up Plan for first-power validation.
Finalize charger and layout
Finalize BQ25750 values
Size supercapacitor bank
Add safety protections
Proceed to placement
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Board Bring-Up Plan — Regenerative Braking Charger
Prerequisites
- Equipment: multimeter, oscilloscope, current-limited bench supply, electronic load or power resistor, insulated wiring, Li-ion-safe charger/test pack, safety glasses.
- Start without the Li-ion battery connected until the rectifier/protection and regulator rails are verified.
- Treat the supercapacitor bank as a high-current energy source; discharge it through the bleeder/load before handling.
1. Visual Inspection
- Verify bridge rectifiers BR1/BR2 orientation and polarity.
- Verify TVS D1 polarity: cathode to
VGEN_PROT, anode toPGND. - Verify supercapacitor bank equivalent C1 polarity/rating if implemented with polarized capacitors.
- Verify battery connector J3 pinout: Pin_1 =
VBAT_2S, Pin_2 =BAT_MID, Pin_3 =PGND. - Verify U4 MIC5365 orientation before applying 5 V.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Measure At | Initial Current Limit | Pass Criteria |
|---|---|---|---|---|---|
VGEN_PROT | BR1/BR2 rectified motor input with TVS/supercap | 0–30 V normal target, transient-clamped | D1 cathode / C1 P1 | 100–300 mA during bench testing | Voltage rises smoothly and clamp does not conduct during normal low-voltage tests |
VBAT_2S | BQ25750 charger / 2S pack | 6.0–8.4 V | J3 Pin_1 to Pin_3 | 100 mA first power-up | No reverse polarity, no excessive current |
+5V | U3 LTC3388 module | 5.0 V | U3 VOUT / J4 5V | 100 mA | 4.75–5.25 V |
+3V3_RFID | U4 MIC5365-3.3YC5 | 3.3 V | U4 VOUT / J6 P1 | 50 mA | 3.2–3.4 V and RC522 VCC is not tied to 5 V |
PGND | Common return | 0 V reference | J3 Pin_3 / J4 GND / J6 P2 | N/A | Continuity across all ground points |
3. First Power-Up Procedure
- With no battery installed, check resistance from
VGEN_PROT,VBAT_2S,+5V, and+3V3_RFIDtoPGND. - Apply a current-limited DC source to one motor input connector through BR1 at low voltage first, then verify
VGEN_PROTpolarity. - Verify the TVS D1 is not hot during normal low-voltage tests.
- Apply a safe 2S battery-equivalent voltage to
VBAT_2Susing a bench supply and verify U3 generates+5V. - Verify U4 generates
+3V3_RFIDfrom+5V. - Connect the LCD only after
+5Vis verified. - Connect the RC522 only after
+3V3_RFIDis verified.
4. Interface Checks
Table
| Interface | Connector | Signals | Pass Criteria |
|---|---|---|---|
| I2C LCD / charger control | J4/J5/U1 | I2C_SDA, I2C_SCL | Pull-ups to +3V3_RFID; logic remains within 3.3 V-safe range |
| RC522 SPI | J6/J5 | SPI_SCK_3V3, SPI_MOSI_3V3, SPI_MISO_3V3, RFID_SS, RFID_RST | All SPI lines swing 0–3.3 V only |
| Battery connector | J3 | VBAT_2S, BAT_MID, PGND | Pinout matches actual 2S pack/BMS wiring |
5. Open Validation Items
- Final BQ25750 external component values, compensation, bootstrap capacitors, feedback network, and charge-current programming must be finalized from the TI datasheet before PCB layout.
- The supercapacitor bank C1 is currently represented as an equivalent bank; final series cell count, balancing, ESR, ripple current, fuse, and discharge timing must be calculated.
- If the LCD module requires 5 V I2C pull-ups, add proper bidirectional level shifting; current schematic keeps shared I2C pull-ups at 3.3 V for IC safety.
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. First Power-Up Procedure
4. Interface Checks
5. Open Validation Items
