Modular Intelligent Lighting Development

ethansol7

ethansol7

The SOLX Rev A PCB has now passed airwire validation and major DRC routing blockers appear resolved.
Prepare a COMPLETE final export and engineering handoff package for Codex and downstream manufacturing workflows.
Do not create placeholder exports. Generate the real finalized package from the current validated board state.
Tasks:
  1. Final validation pass Re-run:
  • Electrical Rule Checks
  • Design Rule Checks
  • Airwire checks
  • Dangling trace checks
  • Under-connected via checks
  • Manufacturing checks
Confirm:
  • airwires = 0
  • no critical DRC blockers
  • no missing footprints
  • no critical copper overlap
  • no invalid layers
  • no critical manufacturing blockers
  1. Generate final manufacturing package Export:
  • Gerber ZIP (RS-274X)
  • NC drill files
  • BOM CSV
  • Pick and Place CSV
  • schematic PDF
  • PCB layout PDF
  • STEP export or 3D board export if available
  • DRC/ERC reports
  • board render screenshots
  1. Generate Codex engineering handoff package Create this exact structure:
SOLX_RevA_Final/ README.md hardware/ gerbers/ drill/ bom/ pick_and_place/ schematic_pdf/ pcb_layout_pdf/ step_export/ drc_reports/ renders/ docs/ SYSTEM_ARCHITECTURE.md PINOUT.md PCB_REV_A_SUMMARY.md MANUFACTURING_CHECKLIST.md VALIDATION_PLAN.md BRINGUP_PROCEDURE.md FIRST_POWER_ON_CHECKLIST.md MODULE_ID_SYSTEM.md POGO_INTERFACE_SPEC.md CHANGELOG.md firmware/ README.md pin_config_template.h module_detection_pseudocode.md esp32_startup_flow.md lawyer_package/ SOLX_Technical_Summary.md SOLX_Interface_Explanation.md SOLX_Module_Identification_Explanation.md SOLX_Patent_Support_Notes.md exports/ screenshots/ renders/ presentation_assets/
  1. Generate engineering summary documents Include:
  • finalized pinout table
  • power architecture summary
  • pogo pass-through explanation
  • module identification explanation
  • resistor ID fallback explanation
  • optional EEPROM identification explanation
  • ESP32 architecture summary
  • future reserved DATA/ID capability explanation
  1. Generate lawyer-friendly technical support material Explain:
  • standardized magnetic electrical interface
  • power and reserved data transfer through stacked modules
  • embedded identification elements
  • module metadata capability
  • configuration recognition
  • future lifecycle/authentication capability
  • modular hardware ecosystem potential
Use broad technical language. Do not use startup marketing language. Do not mention PlastiVista.
  1. Generate manufacturing readiness report Clearly separate:
  • confirmed working architecture
  • assumptions
  • estimated current limits
  • untested features
  • future Rev B recommendations
  • recommended prototype validation sequence
  1. Generate prototype bring-up checklist Include:
  • continuity checks
  • power rail verification
  • regulator verification
  • ESP32 verification
  • pogo continuity testing
  • module stack testing
  • EEPROM/resistor ID testing
  • safe first power-on sequence
  1. Final package requirements The final output package should feel like:
  • a real hardware startup engineering repo
  • suitable for Codex development workflows
  • suitable for PCB manufacturing
  • suitable for engineering collaboration
  • suitable for lawyer review
  • suitable for future firmware development
At the end: Provide:
  • complete export file list
  • manufacturing readiness status
  • recommended next steps
  • what still requires physical prototype validation before production

flux

Final package generated: Download SOLX_RevA_Final.zip, containing real Flux exports: Gerbers, BOM, pick-and-place, PDF, STEP, SVG/GLB renders, DRC/ERC report, firmware handoff, docs, and lawyer package. I followed the manufacturing export gate logic that blocks export on airwires, missing footprints, or critical overlapping copper, and the final review returned no critical checks for the requested blocker categories .
Status: documentation ready, Codex ready, lawyer-review ready, fabrication-quote ready; not automatically approved for prototype ordering until a human EE/mechanical review verifies pogo geometry, connector fit, drill sizes, assembly rotations, and first-article bring-up. Complete file list, readiness report, recommended next steps, and physical validation requirements are included inside the ZIP.
Review exported package
Check BOM completeness
Draft fab email
Create Rev B list
U2
C1
Capacitance
47 uF
J5 1 - J6 1
J5 1 - J6 1
J2 6 - R3 P2
J2 5 - R2 P2
U1 VOUT - C3 P1
J5 5 - J6 5
C4
Capacitance
10 uF
D1 Cathode - U1 VIN
U1 VOUT - C3 P1
J5 5 - J6 5
J2 2 - TP1 P1
D1 Cathode - U1 VIN
U1 VOUT - C3 P1
J5 6 - J6 6
J2 6 - R3 P2
J5 7 - J6 7
J2 6 - R3 P2
J3 1 - J4 1
J3 7 - J4 7
F1 2 - D1 Anode
J5 6 - J6 6
J2 6 - R3 P2
J2 2 - TP1 P1
J5 6 - J6 6
D1 Cathode - U1 VIN
J3 7 - J4 7
J3 5 - J4 5
J5 6 - J6 6
F1 2 - D1 Anode
J1 Center pin - F1 1
J5 1 - J6 1
U1 VOUT - C3 P1
J5 5 - J6 5
U7 VOUT - C5 P1
U1 VOUT - C3 P1
J1 Center pin - F1 1
U7 VOUT - C5 P1
J2 7 - U2 GPIO16
R1 P2 - D2 A
D1 Cathode - U1 VIN
J3 6 - J4 6
U1 VOUT - C3 P1
J3 2 - J4 2
J2 7 - U2 GPIO16
U1 VOUT - C3 P1
C3
Capacitance
10 uF
J2 5 - R2 P2
J2 5 - R2 P2
J2 5 - R2 P2
J5 2 - J6 2
R1 P2 - D2 A
U7 VOUT - C5 P1
C2
Capacitance
10 uF
J3 2 - J4 2
J2 7 - U2 GPIO16
J3 1 - J4 1
J5 1 - J6 1
J3 6 - J4 6
J5 7 - J6 7
C5
Capacitance
10 uF
D1 Cathode - U1 VIN
J3 5 - J4 5
U1 VOUT - C3 P1
J5 2 - J6 2
GND
J5 3 - J6 3
J3 3 - J4 3
J5 3 - J6 3
J3 3 - J4 3
J5 3 - J6 3
J2 4 - TP2 P1
J2 4 - TP2 P1
GND
U3 A2 - U3 WP
J5 3 - J6 3
J5 3 - J6 3
GND
GND
J5 3 - J6 3
J5 3 - J6 3
J3 3 - J4 3
GND
GND
J5 3 - J6 3
U3 A2 - U3 WP
J5 3 - J6 3
J5 3 - J6 3
GND
GND
J3 3 - J4 3
J2 4 - TP2 P1
D1
TP6
J2
TP2
TP5
TP4
TP3
J5
J3
J6
TP1
J4
J1
U7
R2
Resistance
4.7 kΩ
R3
Resistance
4.7 kΩ
U5
U3
R4
Resistance
10 kΩ
U4
D2
R1
Resistance
2.2 kΩ
U6
H1
F1
U1

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SOLX Rev A Routing Execution Plan
Purpose: give a human PCB editor a direct, execution-oriented routing plan for finishing the remaining SOLX Rev A airwires in Flux. This is not an architecture redesign; it is a physical routing sequence for the existing 100 mm × 100 mm, 2-layer proof-of-concept board.
Current verified layout context:
  • Board: 100 mm × 100 mm rectangle, 2-layer stackup.
  • Placement density: low, about 26% component area.
  • Active DRC blocker: 41 airwires.
  • Major placements:
    • Base input/protection: J1 at left edge, F1/D1/U1/C1/C2/C3 around upper-left/mid-left.
    • ESP32 module U2 near upper-center.
    • Base pogo/header interface J2 near upper-right edge.
    • Pass-through pair J3/J4 near upper-right, side-by-side.
    • Smart-ID pair J5/J6 near right-center/lower-right, side-by-side.
    • Smart-ID regulator U7/C4/C5 near J5/J6.
    • I2C EEPROM U3 and R4 near lower-right.
    • Test points mostly on left/upper-mid areas.
Overall routing philosophy
This Rev A board is a proof-of-concept and should be visually understandable. Favor direct, readable routes over aggressive optimization.
Use:
  • Top layer: primary routing, component-side traces, short point-to-point routes.
  • Bottom layer: broad GND return where possible, longer horizontal/vertical jump routes, and limited crossovers.
  • Copper pours: GND pour on both layers after signal/power routing, stitched with vias.
  • Vias: acceptable for low-speed signals and power transitions, but keep them intentional and sparse.
Recommended default constraints:

Table

Net classSuggested widthSuggested clearanceVia guidance
12V input/protected power0.75–1.00 mm≥0.25 mmAvoid where possible; if needed use 2 vias in parallel
Pogo 12V pass-through rails0.75–1.00 mm≥0.25 mmAvoid between mating pads; use direct top-side routes
GND trunkscopper pour + 0.75–1.00 mm traces≥0.25 mmUse stitching vias; multiple vias for current returns
3.3V logic rail0.30–0.50 mm≥0.20 mmSingle via acceptable
DATA/SDA, ID/SCL, DETECT0.20–0.25 mm≥0.20 mmSingle via acceptable; keep clean and away from 12V trunks
EEPROM local I2C0.20–0.25 mm≥0.20 mmPrefer top layer, short traces
LED/test point branches0.20–0.30 mm≥0.20 mmFlexible
Do not use 0.15 mm traces unless absolutely necessary. A Rev A prototype should be easy for common PCB fabs.
1. Critical power nets
VIN_JACK: J1 center pin → F1:1
Route first. This is the raw DC input from the barrel jack.
  • Preferred layer: top.
  • Width: 0.75–1.00 mm.
  • Path: short direct segment from J1 to F1.
  • Vias: avoid.
  • Geometry: keep it wide and visible; this is the start of the current path.
  • Keepout: maintain clearance from mounting holes and test points.
VIN_FUSED: F1:2 → D1 anode
Route immediately after VIN_JACK.
  • Preferred layer: top.
  • Width: 0.75–1.00 mm.
  • Path: direct from fuse output to reverse-protection diode anode.
  • Vias: avoid.
  • Reason: keeps the protection chain visually obvious: input → fuse → reverse protection.
12V_PROTECTED: D1 cathode → U1 VIN → C1/C2 → J2 pins 1/2 → TP1
This is the most important power distribution net on the base controller.
  • Preferred layer: top for main trunk; bottom only if needed for a clean jumper.
  • Width:
    • Main trunk D1 cathode to J2 pins 1/2: 1.00 mm where possible.
    • Branch to U1 VIN and capacitors: 0.50–0.75 mm.
    • Branch to TP1: 0.30–0.50 mm.
  • Vias: avoid on main trunk. If a layer transition is unavoidable, use two vias in parallel for the 12V trunk.
  • Routing strategy:
    1. Route D1 cathode to a 12V trunk running toward J2.
    2. Branch down/sideways to U1 VIN and C1/C2.
    3. Connect J2 pins 1 and 2 with a short local copper link or fat trace near J2.
    4. Add TP1 as a small branch, not inline with main current.
  • Keep 12V_PROTECTED away from DATA_SDA and ID_SCL by at least normal clearance; more if space allows.
SID_12V_A: J5:1 → J6:1 → U7 VIN → C4:P1
This powers the Smart ID Test Module local regulator and demonstrates 12V pass-through.
  • Preferred layer: top.
  • Width: 0.75–1.00 mm between J5/J6 and U7 VIN; 0.50 mm to C4.
  • Vias: avoid.
  • Routing strategy:
    • Because J5 and J6 are side-by-side, route pin 1 as a straight horizontal or short U-shaped top trace between the matching pins.
    • Take a branch from that pass-through route to U7 VIN and C4.
    • Do not make U7 VIN the middle of the pass-through path; pass-through should remain clear and direct.
SID_12V_B: J5:2 → J6:2
This is the duplicated 12V contact path for reliability/current margin.
  • Preferred layer: top.
  • Width: 0.75–1.00 mm.
  • Vias: avoid.
  • Routing strategy: direct short link between matching pogo contacts.
  • Keep parallel to SID_12V_A if possible, with clear spacing and consistent orientation.
PT_12V_A: J3:1 → J4:1
Pass-through module 12V rail A.
  • Preferred layer: top.
  • Width: 0.75–1.00 mm.
  • Vias: avoid.
  • Routing strategy: short direct link between the matching pins of J3 and J4.
PT_12V_B: J3:2 → J4:2
Pass-through module duplicated 12V rail B.
  • Preferred layer: top.
  • Width: 0.75–1.00 mm.
  • Vias: avoid.
  • Routing strategy: short direct link between matching pins, visually parallel to PT_12V_A.
2. Ground returns
GND net: all ground pins, capacitors, J2 pins 3/4, J3/J4 pins 3/4, J5/J6 pins 3/4, U1/U7 GND, U2 GND, U3 GND/EP, D2 cathode, TP2
Route ground second, before low-speed signals.
  • Preferred implementation: GND copper pour on both layers, with direct short traces where pour may not reach.
  • Pour strategy:
    • Add or preserve a bottom-layer GND pour across the board.
    • Add a top-layer GND pour if Flux supports it without creating overlaps.
    • Keep the pour connected around the board; do not split the GND plane with long 12V traces.
  • Trace width where explicit traces are needed: 0.75–1.00 mm for power return paths; 0.30–0.50 mm for local signal/reference branches.
  • Vias:
    • Use GND stitching vias near U1, U7, J2, J3/J4, J5/J6, and around the ESP32 module.
    • Use at least one GND via near any signal via.
    • Use multiple GND vias around duplicated pogo GND contacts if they route through the bottom layer.
  • Decoupling priority:
    • C1/C2/C3 should have very short GND return to U1 and the local GND pour.
    • C4/C5 should have very short GND return to U7 and local GND pour.
    • U3 GND and EP should connect to the nearest GND pour with short top trace and/or via.
Ground routing order:
  1. Connect J1 terminal to the main GND pour/return.
  2. Connect U1 GND, C1/C2/C3, and U2 GND pins.
  3. Connect J2 pins 3/4 to the GND pour with fat local copper.
  4. Connect pass-through GND pins J3/J4 pins 3/4 with direct short links.
  5. Connect smart-ID GND pins J5/J6 pins 3/4 with direct short links.
  6. Connect U7/C4/C5/U3/R4/D2/TP2.
3. ESP32 support traces
U2 ESP32 routing should be readable and not forced through the antenna area. If the ESP32 module footprint has an antenna end, keep copper and routing away from that keepout region.
3V3_BASE: U1 VOUT → C3 → U2 3V3 → R1/R2/R3 → TP3 → U2:VP
  • Preferred layer: top.
  • Width:
    • U1 VOUT to U2 3V3/C3: 0.50 mm.
    • Pull-up resistor branches and TP3: 0.25–0.30 mm.
  • Vias: acceptable but avoid if a direct top-side route is easy.
  • Routing strategy:
    1. Route U1 VOUT to C3 first.
    2. Route from C3/U1 output node to U2 3V3.
    3. Branch to R1/R2/R3 and TP3 from the 3.3V rail.
    4. U2:VP is tied to 3V3_BASE as an intentional defined state; route it as a short branch if the pin is physically nearby. If not nearby, one via is acceptable.
  • Keep short: U1 VOUT to C3; C3 to U1/U2 supply path.
DATA_SDA: U2 GPIO21 → J2:5 → R2:P2 → TP4
  • Preferred layer: top for U2-to-J2 and R2 pull-up branch.
  • Width: 0.20–0.25 mm.
  • Vias: one via acceptable if crossing the 12V trunk would otherwise be messy.
  • Keep away from: 12V high-current trunk and noisy input/protection region.
  • Routing priority: clean geometry over shortest path; this is low-speed I2C/reserved data.
  • Pull-up R2 should connect as a short branch to the line, not force the signal to route through the resistor body.
ID_SCL: U2 GPIO22 → J2:6 → R3:P2 → TP5
  • Preferred layer: top.
  • Width: 0.20–0.25 mm.
  • Vias: one acceptable.
  • Routing: keep parallel-ish to DATA_SDA with modest spacing; do not require length matching.
  • Keep away from: 12V input/protection chain.
  • Pull-up R3 should be a short branch.
DETECT: U2 GPIO16 → J2:7 → TP6
  • Preferred layer: top.
  • Width: 0.20–0.25 mm.
  • Vias: one acceptable.
  • Routing: simple direct GPIO route from U2 to J2 pin 7, with TP6 branch near accessible edge/area.
  • Signal integrity: low-speed digital presence line; no length matching needed.
4. Pogo interface routing strategy
The board uses 7-contact interfaces, with duplicated power and ground contacts for reliability. The routing should reinforce this concept visually.
Recommended physical contact order:
  1. 12V_A
  2. 12V_B
  3. GND_A
  4. GND_B
  5. DATA/SDA
  6. ID/SCL
  7. DETECT/PRESENCE
For each mating pair J3/J4 and J5/J6:
  • Route same-numbered pins directly and in parallel where possible.
  • Keep the top-side pass-through traces short and easy to inspect.
  • Do not weave the pass-through routes through unrelated circuitry.
  • Preserve consistent orientation: pin 1 on bottom/top interfaces should correspond to the same physical side.
  • Place or verify silkscreen labels at each contact: 12V_A, 12V_B, GND_A, GND_B, DATA, ID, DETECT.
Power/gnd pad geometry:
  • 12V and GND traces should be wider than signal traces.
  • If pad size permits, connect duplicated 12V and duplicated GND contacts with wide local copper.
  • Avoid thermal relief on pogo current pads if they are purely surface pads and hand soldering is not a concern; if Flux/fab defaults apply thermal relief, verify current path is still adequate.
5. Reserved DATA/ID lines
Base DATA_SDA and ID_SCL
  • DATA_SDA and ID_SCL are reserved communication lines from ESP32 to the base pogo interface.
  • Keep them as a recognizable pair from U2 to J2 pins 5/6.
  • Width: 0.20–0.25 mm.
  • Clearance: ≥0.20 mm; use ≥0.30 mm from 12V if space allows.
  • Vias: acceptable, but do not use unnecessary zig-zag transitions.
  • No impedance control needed for Rev A low-speed I2C/metadata testing.
Pass-through PT_DATA_SDA and PT_ID_SCL
  • J3:5 → J4:5 and J3:6 → J4:6.
  • Preferred layer: top.
  • Width: 0.20–0.25 mm.
  • Vias: avoid if possible.
  • Strategy: route parallel short links between connector pairs.
  • Do not cross under/through power pads if a clean perimeter route is possible.
Smart-ID SID_DATA_SDA and SID_ID_SCL
  • SID_DATA_SDA: J5:5, J6:5, U3:SDA.
  • SID_ID_SCL: J5:6, J6:6, U3:SCL, R4:P1.
  • Preferred layer: top.
  • Width: 0.20–0.25 mm.
  • Vias: avoid for local U3 routes unless escaping around J5/J6 requires one.
  • Strategy:
    • First link J5/J6 same-numbered pins.
    • Then branch to U3 SDA/SCL.
    • R4, if used as a resistor-ID/pull element, should branch cleanly from the ID/SCL line.
6. LED/output paths
PWR_LED: R1:P2 → D2:A
  • Preferred layer: top.
  • Width: 0.20–0.30 mm.
  • Vias: avoid.
  • Routing: very short direct trace; this is non-critical.
D2 cathode to GND
  • Prefer top trace to nearby GND pour or direct GND via.
  • Width: 0.20–0.30 mm.
  • Keep LED trace readable so the power indicator function is obvious.
7. Test point routing
Test points should be branches, not series elements.
  • TP1: branch from 12V_PROTECTED. Width 0.30–0.50 mm.
  • TP2: branch to GND pour. Use short trace/via.
  • TP3: branch from 3V3_BASE. Width 0.25–0.30 mm.
  • TP4: branch from DATA_SDA. Width 0.20–0.25 mm.
  • TP5: branch from ID_SCL. Width 0.20–0.25 mm.
  • TP6: branch from DETECT. Width 0.20–0.25 mm.
Keep test point branches short and label them clearly. Avoid placing test point branches through critical current paths.
8. Optional EEPROM / identification traces
SID_3V3: U7 VOUT → C5 → U3 VCC
  • Preferred layer: top.
  • Width: 0.30–0.50 mm.
  • Vias: avoid.
  • Keep short: U7 VOUT to C5 and U3 VCC.
  • Treat this as a local regulator output island, not a board-wide rail.
U3 local ground and address pins
  • U3 GND, EP, A0, A1, A2, WP should tie directly into local GND.
  • Preferred: short top traces to GND pour or a nearby GND via.
  • Keep these traces short and visually grouped with U3.
R4 on SID_ID_SCL
  • If R4 is resistor-ID fallback/pull element, route it as a branch from SID_ID_SCL to GND.
  • Width: 0.20–0.25 mm.
  • Keep close to U3/J5/J6 so its function is obvious.
Follow this exact order in the Flux PCB editor:
  1. Pre-routing cleanup
    • Check for dangling traces/stubs and remove them before new routing.
    • Verify no components overlap.
    • Confirm board outline is visible and closed.
  2. Input protection chain
    • VIN_JACK: J1 center → F1:1.
    • VIN_FUSED: F1:2 → D1 anode.
    • 12V_PROTECTED: D1 cathode → U1 VIN/C1/C2 → J2 pins 1/2 → TP1.
  3. Base ground and 3.3V
    • GND around J1/U1/C1/C2/C3/U2/J2.
    • 3V3_BASE from U1 VOUT/C3 to U2 3V3, R1/R2/R3, TP3, U2:VP.
  4. Base ESP32 to pogo interface
    • DATA_SDA: U2 GPIO21 → J2:5, with R2 and TP4 branch.
    • ID_SCL: U2 GPIO22 → J2:6, with R3 and TP5 branch.
    • DETECT: U2 GPIO16 → J2:7, with TP6 branch.
  5. Pass-through module interface J3/J4
    • PT_12V_A and PT_12V_B.
    • GND pins 3/4.
    • PT_DATA_SDA, PT_ID_SCL, PT_DETECT.
  6. Smart-ID module interface J5/J6
    • SID_12V_A and SID_12V_B.
    • GND pins 3/4.
    • SID_DATA_SDA, SID_ID_SCL, SID_DETECT.
  7. Smart-ID local regulator and EEPROM
    • SID_12V_A branch to U7 VIN/C4.
    • SID_3V3 from U7 VOUT/C5 to U3 VCC.
    • U3 SDA/SCL to J5/J6 data/ID lines.
    • U3 address/WP/EP/GND to local ground.
  8. Indicator and remaining test point branches
    • PWR_LED and D2 ground.
    • Any remaining TP branches.
  9. Copper pours and stitching
    • Apply GND pours on bottom, then top if available.
    • Add stitching vias near connectors, regulators, and around board perimeter.
    • Refill pours and re-run DRC.
Suggested DRC constraints before final routing
Use conservative prototype settings:
  • Minimum signal trace width: 0.20 mm.
  • Preferred signal trace width: 0.25 mm.
  • 3.3V trace width: 0.30–0.50 mm.
  • 12V/pogo current trace width: 0.75–1.00 mm.
  • Minimum copper clearance: 0.20 mm.
  • Preferred power clearance: 0.25 mm or greater.
  • Via drill: 0.30 mm minimum for general use.
  • Power via drill: 0.40 mm if carrying 0.5–1 A; use multiple vias for higher current.
  • Copper-to-board-edge clearance: ≥0.30 mm, preferably ≥0.50 mm for Rev A.
Signal integrity considerations
This is a low-speed 2-layer prototype, so the main SI concern is clean return paths, not impedance control.
  • Keep DATA_SDA and ID_SCL over or near continuous GND where possible.
  • Avoid routing DATA/ID directly alongside 12V for long distances.
  • If a DATA/ID trace changes layers, place a GND stitching via nearby.
  • Keep U1/U7 regulator input/output capacitors close and with short GND paths.
  • Keep ESP32 antenna area free of copper/traces if the footprint/module has a PCB antenna keepout.
  • No length matching is required for DATA_SDA and ID_SCL in this Rev A implementation.
Copper pour strategy
  1. Finish all intentional routed traces first.
  2. Add/refill a bottom-layer GND pour across the board.
  3. Add/refill a top-layer GND pour only if it does not create confusing islands near pogo pads.
  4. Stitch GND between layers near:
    • J1 input connector.
    • U1/C1/C2/C3.
    • U2 GND pins.
    • J2 pogo/header output.
    • J3/J4 pass-through connectors.
    • J5/J6 smart-ID connectors.
    • U7/C4/C5/U3.
  5. Remove isolated copper islands if DRC flags floating copper.
  6. Keep 12V pours optional. For Rev A, wide traces are easier to review than large unlabeled 12V copper areas.
Board cleanup process after routing
After all visible ratsnest/airwires are gone:
  1. Re-run airwire DRC.
  2. If any airwire remains, click it and route that specific pad-to-pad connection manually.
  3. Refill GND pours.
  4. Run DRC for:
    • Airwires.
    • Overlapping copper.
    • Invalid layer.
    • Dangling trace.
    • Missing footprints.
    • Clearance / drill spacing.
  5. Fix in this order:
    1. Invalid layers.
    2. Overlaps/shorts.
    3. Clearance/drill issues.
    4. Dangling traces.
    5. Remaining airwires.
    6. Silkscreen issues.
  6. Confirm silkscreen labels for all pogo contacts and power polarity.
  7. Confirm board outline is closed and mounting holes are correct.
Final pre-Gerber checklist
Do not export fabrication files until all critical items below are true:
  • Airwires = 0.
  • No overlapping copper on different nets.
  • No invalid layer errors.
  • No missing footprints.
  • No critical clearance violations.
  • No dangling traces.
  • Board outline closed.
  • Mounting holes have valid drill definition and adequate copper clearance.
  • Pogo contacts/pads are labeled and orientation is consistent.
  • 12V and GND duplicated contacts are routed with wide copper.
  • U1/U7 capacitors have short input/output/GND routes.
  • ESP32 antenna region is not blocked by copper if applicable.
  • BOM still excludes fabricated test pads and mounting holes.
  • Gerber, drill, BOM, pick-place, schematic PDF, layout PDF, and STEP export are generated only after checks pass.
Human routing shortcut
Because the board has generous space, the fastest clean manual route is:
  1. Route all connector-pair pass-through links J3↔J4 and J5↔J6 first as short parallel traces.
  2. Route the base input power chain J1→F1→D1→U1/J2.
  3. Pour GND and connect local GND pads with short spokes/vias.
  4. Route ESP32 GPIO lines to J2.
  5. Route U7/U3 local smart-ID circuit.
  6. Finish test point branches.
  7. Run DRC and clean the few leftovers.
This should be achievable quickly because most remaining nets are either short connector-pair pass-throughs or low-speed support signals, not dense fine-pitch routing.

  • Overall routing philosophy

  • 1. Critical power nets

  • VIN_JACK: J1 center pin → F1:1

  • VIN_FUSED: F1:2 → D1 anode

  • 12V_PROTECTED: D1 cathode → U1 VIN → C1/C2 → J2 pins 1/2 → TP1

  • SID_12V_A: J5:1 → J6:1 → U7 VIN → C4:P1

  • SID_12V_B: J5:2 → J6:2

  • PT_12V_A: J3:1 → J4:1

  • PT_12V_B: J3:2 → J4:2

  • 2. Ground returns

  • GND net: all ground pins, capacitors, J2 pins 3/4, J3/J4 pins 3/4, J5/J6 pins 3/4, U1/U7 GND, U2 GND, U3 GND/EP, D2 cathode, TP2

  • 3. ESP32 support traces

  • 3V3_BASE: U1 VOUT → C3 → U2 3V3 → R1/R2/R3 → TP3 → U2:VP

  • DATA_SDA: U2 GPIO21 → J2:5 → R2:P2 → TP4

  • ID_SCL: U2 GPIO22 → J2:6 → R3:P2 → TP5

  • DETECT: U2 GPIO16 → J2:7 → TP6

  • 4. Pogo interface routing strategy

  • 5. Reserved DATA/ID lines

  • Base DATA_SDA and ID_SCL

  • Pass-through PT_DATA_SDA and PT_ID_SCL

  • Smart-ID SID_DATA_SDA and SID_ID_SCL

  • 6. LED/output paths

  • PWR_LED: R1:P2 → D2:A

  • D2 cathode to GND

  • 7. Test point routing

  • 8. Optional EEPROM / identification traces

  • SID_3V3: U7 VOUT → C5 → U3 VCC

  • U3 local ground and address pins

  • R4 on SID_ID_SCL

  • Recommended routing order

  • Suggested DRC constraints before final routing

  • Signal integrity considerations

  • Copper pour strategy

  • Board cleanup process after routing

  • Final pre-Gerber checklist

  • Human routing shortcut

Documents

Assets

Assets are files uploaded to this project which can be used in various ways.

SOLX Rev A Modular Lamp PCB POC thumbnail
Manufacturable Rev A proof-of-concept PCB system for the SOLX modular magnetic lamp platform, documenting a standardized magnetic pogo-pin electrical pass-through interface, 12V low-voltage power transfer, reserved data/ID contacts, module identification support, automatic configuration recognition, lifecycle metadata tracking capability, and patent-supporting manufacturing/test documentation.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$7.70–$8.01

Digi-Key

$11.42–$12.13

HQonline

$0.88–$0.99

LCSC

$26.54–$26.67

Mouser

$13.22–$13.28

TME

$1.18

Verical

$0.87–$1.65

Controls