# \[Multi\-layer\] JLCPCB Constraints \- test

## Description

Use this template if you're planning to get your multi layer board manufactured in JLCPCB\. It has the via min/max and trace width constraints already baked as global rules\. \#project\-template \#template \#manufacturer\-design\-rules

## Project Details

- **Owner:** eric\-test\-org
- **Created:** 1/19/2024
- **Last Updated:** 1/19/2024
- **Visibility:** Public
- **Board Thickness:** 1\.6mm
- **Copies:** 1

*The full schematic, PCB layout, bill of materials, and interactive design are available at [https://flux\.ai/eric\-test\-org/multi\-layer\-jlcpcb\-constraints\-test\~p5](https://flux.ai/eric-test-org/multi-layer-jlcpcb-constraints-test~p5).*

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*Generated from [https://flux\.ai/eric\-test\-org/multi\-layer\-jlcpcb\-constraints\-test\~p5](https://flux.ai/eric-test-org/multi-layer-jlcpcb-constraints-test~p5)*