Mini UPS PCB Design

flux

0:59

Considering tool usage for issues.

Running design review.

Analyzing the schematic.

Addressing power output concerns.

Running design review.

I fixed the actionable ERC issues and checked ERC again.
What I fixed
  • Added intentional no-connect markers to the unused status pins on U1 and U2
  • Added intentional no-connect markers to the isolated mounting holes H1, H2, H3, and H4
That cleared all the floating-pin warnings. Using the review tool is the correct way to check ERC/DRC status, and those checks update automatically in Flux
Current ERC result Remaining issue
  • Power input not driven: U3 VCC on HV_BUS
What this means
This remaining ERC error is not necessarily a real wiring mistake.
Right now HV_BUS is fed through the ideal-diode path:
ERC is looking for a pin typed as a formal power-output driver. In this topology, the bus is being supplied through analog power-path parts, so ERC may not recognize that as a conventional driven power source even though the connectivity is valid. The project inspection tools are the right source for confirming the actual net connections

Status summary

CheckStatus
Floating pinsFixed
No-connect violationsClean
Pin-to-pin conflictsClean
Shorted componentsClean
Undriven netsClean
Single-pin netsClean
Missing power on U3 VCCStill flagged
Practical recommendation
At this point:
  • the review noise is cleaned up
  • the only remaining ERC item is the U3 power-source classification issue
If you want, I can do one of these next:
  1. Inspect the exact HV_BUS path around U1, U2, Q1, Q2, and U3 and tell you whether the remaining ERC error is safe to ignore
  2. Help you fix the remaining schematic-quality issues beyond ERC, like net naming and final connection cleanup
Inspect HV_BUS path
Clean schematic issues
Check if safe
7 days

Applied changes.

0:02

nets {

net BATTERY_IN = Q2:S, R3:P1, R4:P1, U2:IN, C2:P1, F2:2;

net GND = D3:A, J4:PIN2, J3:Neg, R5:P2, U3:GND, C8:P2, R6:P2, C3:P2, Q4:E, C1:P2, Q3:E, C2:P2, C4:P2, C7:P2, U2:GND, U2:OFF, J2:Terminal, U1:GND, U1:OFF, J1:Terminal, R1:P2, D2:A, D1:A;

net Net 2 = U2:GATE, Q2:G;

net ADAPTER_IN = R2:P1, R8:P1, Q1:S, F1:2, C1:P1, U1:IN;

net HV_BUS = C4:P1, C3:P1, Q1:D, U1:OUT, U3:EN, U3:VCC, U2:OUT, Q2:D;

net gate_driver_mosfet_1 = Q1:G, U1:GATE;

}

7 days
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Design Notes
Scope
Design a mini UPS PCB that accepts:
  • External 42 V adapter input
  • External 10S lithium battery pack input (30 V to 42 V nominal operating range with pack/BMS external)
The board shall:
  • Prioritize the adapter when present
  • Automatically switch to the battery when the adapter is absent or lower than the battery path
  • Generate an HV_BUS in the 30 V to 42 V range
  • Regulate HV_BUS down to 12 V for the output stage
  • Include status LEDs for source indication
  • Include battery monitor pads for external sensing
The board shall NOT include:
  • Onboard battery charging circuitry
  • Battery pack design
  • Adapter power supply design
Functional Blocks
  1. Adapter Input
  2. Battery Input
  3. Protection and reverse/current blocking
  4. Ideal-diode OR-ing / automatic switchover
  5. HV_BUS (30 V to 42 V)
  6. 12 V buck output stage
  7. Monitoring and status indicators
Initial Design Choices
  • Use ideal-diode controllers with external MOSFETs rather than Schottky OR-ing to minimize loss.
  • Use a synchronous buck stage for 12 V generation from the 30 V to 42 V bus.
  • Use TVS + fuse protection on both external high-voltage inputs.
  • Use a 4-layer PCB as the default safer option for power integrity and routing flexibility.
Open Implementation Assumptions
  • Continuous 12 V output target assumed at up to 2 A based on prior discussion.
  • External battery pack includes its own BMS/protection.
  • Battery monitor pads are voltage-monitor taps only unless a future current-sense stage is added.
Implemented Schematic Snapshot
  • Adapter input is J1 through F1 and D1 into U1 and Q1.
  • Battery input is J3 through F2 and D2 into U2 and Q2.
  • The shared HV bus feeds U3 with local bypass C3 and C4.
  • The 12 V output stage uses L1, C7, C8, R6, and R7.
  • Monitor pads J4 and J5 expose battery positive and ground.

    Scope

    Functional Blocks

    Initial Design Choices

    Open Implementation Assumptions

    Implemented Schematic Snapshot

Documents

    Design Notes

Assets

Assets are files uploaded to this project which can be used in various ways.

Mini UPS 42V to 12V thumbnail
Mini UPS PCB for a 42 V external adapter and external 10S lithium battery pack. Includes adapter-priority source selection with automatic switchover, input protection, ideal-diode OR-ing, a 30 V to 42 V HV bus, and a regulated 12 V output stage. Includes status LEDs and battery monitor pads. Excludes onboard charger circuitry and excludes adapter or battery source design.

Properties

Pricing & Availability

Distributor

Qty 1

Arrow

$39.97–$40.80

Digi-Key

$1.75–$2.47

LCSC

$17.95–$17.97

Mouser

$42.87

TME

$0.43

Verical

$0.97–$2.63

Controls