INA219 Current Measurement Audit

P

piero789

AUDIT AND FIX ONLY THE PCB ROUTING AROUND Q2 INPUT REVERSE-POLARITY PROTECTION.
Context: The schematic has just been corrected:
  • Q2:D -> VIN_FUSED
  • Q2:S -> VIN_PROTECTED
  • Q2:G -> VIN_GATE
  • D6:K -> VIN_PROTECTED
  • D6:A -> VIN_GATE
  • R5 from VIN_GATE to GND
  • R6 between VIN_PROTECTED and VIN_GATE
Task:
  1. Review the PCB layout only around Q2, F2, D3, D6, R5, R6, C7, FB2, and the nets VIN_RAW, VIN_FUSED, VIN_PROTECTED, VIN_GATE, GND.
  2. Remove any stale traces caused by the Q2 source/drain swap.
  3. Reroute Q2 input-protection traces so the physical PCB matches the corrected schematic.
  4. Keep the current protection sequence: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.
  5. Keep Q2, D3, C7, and FB2 routing reasonably short and direct.
  6. Do not modify ESP32, relay, INA219, buck output, RELAY_OUT, or dry-contact nets.
  7. Do not perform a full board redesign yet.
After fixing:
  • Run DRC.
  • Confirm there are no airwires in the Q2/F2/D3/D6/R5/R6/C7/FB2 input-protection area.
  • Confirm there are no dangling traces in the Q2 input-protection area.
  • Report the exact physical routing path from J1 P1 to U1 VIN after the fix.
  • Confirm again that reverse-polarity input cannot energize VIN_PROTECTED or 5V.

flux

I've made a plan and started work on it.

Started implementing a plan

#Goal

- Audit and fix the PCB routing around the Q2 input reverse-polarity protection stage based on the schematic correction, concentrating only on Q2, F2, D3, D6, R5, R6, C7, FB2 and nets VIN_RAW, VIN_FUSED, VIN_PROTECTED, VIN_GATE, and GND. The goal is to remove stale traces from the Q2 source/drain reversal and reroute the protected input path so that it physically follows the path: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED, while ensuring the routing remains short and direct without impacting other nets (ESP32, relay, INA219, buck output, RELAY_OUT, dry-contact).

#Implementation plan

1. **Audit and Cleanup**

1. Inspect the existing PCB layout in the Q2 input reverse-polarity area to identify stale traces and artifacts from the old Q2 source/drain swap.

2. Remove or sever stale traces that connect the Q2 source/drain paths from previous routing.

2. **Reroute Input-Protected Path**

1. Reroute the protected input path to ensure the physical trace follows: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.

2. Maintain a short and direct routing while connecting the nets correctly.

3. Preserve the integrity of other nets and components including ESP32, relay, INA219, buck output, RELAY_OUT, and dry-contact.

3. **DRC Verification and Reporting**

1. Run a targeted Design Rule Check (DRC) focusing on the audited area to ensure clearance and connectivity rules are met.

2. Document and report the exact physical routing path and confirm that the reverse-polarity protection works as intended (i.e. reverse-polarity does not pass through VIN_PROTECTED into the remainder of the circuit).

#Success criteria

- All stale traces from the Q2 source/drain swap are removed without affecting other board areas.

- The physical routing path exactly follows J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED, ensuring short and direct routing.

- DRC reports no violations in the scoped area and confirm reverse-polarity behavior as expected.

- The protected input path prevents undesired conduction during reverse polarity events.

Task unable to complete.

2:13

Thought for 16 sec — Identifying necessary skills
Looking up PCB routing cleanup stale traces Q2 reverse polari....
Checking 5 design areas.
Reading schematic details for J1, F2, Q2 and 7 more.
Completed 5 design checks — found 39 issues.
Checking 5 design areas... (28 sec)
Reading layout details for Q2, F2, D3 and 5 more.

flux

Work done
  • Audited the scoped Q2 input-protection area and verified the corrected schematic connectivity.
  • DRC still reports scoped layout problems: VIN_FUSED airwire between F2:P2 and Q2:D, VIN_PROTECTED airwires involving Q2:S, D6:K, and R6:P2, plus stale/dangling trace remnants and an overlap at Q2:D.
  • Created the detailed status file: Q2 Input Protection Routing Remediation Status.
Success criteria review
  • ❌ Stale traces were identified but not removed in this run.
  • ❌ The physical path is not yet fully routed as J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.
  • ❌ DRC is not clean in the scoped area; airwires/dangling/overlap issues remain.
  • ✅ The corrected schematic topology still supports reverse-polarity blocking, but the PCB must be cleaned/rerouted before fabrication.
Next steps
Perform the physical trace cleanup/reroute in the PCB editor for the listed scoped items, then rerun DRC to confirm the Q2 input-protection area is clear.
Locate routing issues
Fix Q2 remnants
Route VIN_PROTECTED
Run targeted DRC
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Files

Schematic

Layout

Preview

U2
U6
Design Notes
12V-24V Input Protection Stage
A robust input protection block was integrated ahead of J1 and the existing U1 VIN path.
Protection ordering
  • Connector -> PPTC fuse -> P-channel MOSFET reverse-polarity stage -> TVS clamp and ceramic bypass -> ferrite bead -> LM2596 VIN
This follows the recommended protection sequence so sustained faults are current-limited before the surge clamp and reverse-polarity stage, while downstream U1, U2, U6, K1, and RELAY_OUT behavior remain unchanged.
Selected components actually added
  • F1: SMD1206P075TF/30 PPTC fuse, 30 V / 0.75 A hold resettable input protection
  • Q3: QM6015D P-channel MOSFET, 60 V, 25 mOhm typical on-resistance, used as ideal-diode reverse-polarity element
  • D5: SMBJ26A-13-F unidirectional TVS across protected VIN to GND
  • D6: 15 V zener gate-source clamp for Q3
  • FB2: MPZ1005S121HT000 ferrite bead between protected input reservoir and filtered VIN feeding U1
  • C7: 100 nF, 100 V ceramic bypass from protected VIN to GND
  • R5: 100 k gate pull-down to GND
  • R6: 100 k gate-source bias resistor
Net integration
  • VIN_RAW: J1 positive input to F1
  • VIN_FUSED: F1 output to Q3 source
  • VIN_PROTECTED: Q3 drain feeding D5, C7, FB2, and R6
  • VIN_GATE: Q3 gate with R5, R6, and D6
  • VIN_FILTERED: FB2 output feeding U1 VIN, C1, and C3
Placement priorities
  • F1, Q3, D5, and C7 should sit immediately behind J1
  • Keep the surge loop short: J1 -> D5 -> GND return
  • Place FB2 and C3 close to U1 VIN
  • Keep the protected input path physically separate from relay contact routing to preserve dry-contact behavior at RELAY_OUT
Verification criteria
  • Correct-polarity 12 V-24 V input powers the existing buck path with low drop through Q3
  • Reverse-polarity input keeps Q3 off and prevents downstream energization
  • Surge events are clamped by D5 without altering relay dry-contact behavior
  • Existing 5 V regulation and ESP32/INA219/relay functions remain unchanged
  • ERC review after the change shows no new undriven-net, single-pin-net, or missing-power errors in the modified section

  • 12V-24V Input Protection Stage

  • Protection ordering

  • Selected components actually added

  • Net integration

  • Placement priorities

  • Verification criteria