INA219 Current Measurement Audit
Started implementing a plan
#Goal
- Audit and fix the PCB routing around the Q2 input reverse-polarity protection stage based on the schematic correction, concentrating only on Q2, F2, D3, D6, R5, R6, C7, FB2 and nets VIN_RAW, VIN_FUSED, VIN_PROTECTED, VIN_GATE, and GND. The goal is to remove stale traces from the Q2 source/drain reversal and reroute the protected input path so that it physically follows the path: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED, while ensuring the routing remains short and direct without impacting other nets (ESP32, relay, INA219, buck output, RELAY_OUT, dry-contact).
#Implementation plan
1. **Audit and Cleanup**
1. Inspect the existing PCB layout in the Q2 input reverse-polarity area to identify stale traces and artifacts from the old Q2 source/drain swap.
2. Remove or sever stale traces that connect the Q2 source/drain paths from previous routing.
2. **Reroute Input-Protected Path**
1. Reroute the protected input path to ensure the physical trace follows: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.
2. Maintain a short and direct routing while connecting the nets correctly.
3. Preserve the integrity of other nets and components including ESP32, relay, INA219, buck output, RELAY_OUT, and dry-contact.
3. **DRC Verification and Reporting**
1. Run a targeted Design Rule Check (DRC) focusing on the audited area to ensure clearance and connectivity rules are met.
2. Document and report the exact physical routing path and confirm that the reverse-polarity protection works as intended (i.e. reverse-polarity does not pass through VIN_PROTECTED into the remainder of the circuit).
#Success criteria
- All stale traces from the Q2 source/drain swap are removed without affecting other board areas.
- The physical routing path exactly follows J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED, ensuring short and direct routing.
- DRC reports no violations in the scoped area and confirm reverse-polarity behavior as expected.
- The protected input path prevents undesired conduction during reverse polarity events.
Task unable to complete.
2:13
F2:P2 and Q2:D, VIN_PROTECTED airwires involving Q2:S, D6:K, and R6:P2, plus stale/dangling trace remnants and an overlap at Q2:D.J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.Design modification status: Audit/test documentation only. This plan does not modify the schematic, PCB, BOM, or layout.
RELAY_OUT as a dry-contact output only. It must not generate voltage by itself.RSHUNT = 0.22 ohm.BUCK_5V and ESP32_EXT_5V, labelled:Safety Rules Before Starting
Recommended Equipment
1. Visual Inspection Before Power
2. Continuity Test With Multimeter Before Power
3. Dry-Contact Isolation Test
4. Reverse-Polarity Input Test
5. 12V Power-Up Test
6. 24V Power-Up Test
7. 5V Rail Voltage and Ripple Check
8. ESP32 Boot Test
9. Relay Activation Test From GPIO23
10. INA219 Current Reading Test
11. RELAY_OUT Continuity Test When Relay Off/On
12. Confirm No Voltage Is Generated on RELAY_OUT by the PCB
13. USB / Back-Power Safety Test or Warning Procedure
14. Long Pulse / Repeated Pulse Thermal Test
15. Final Machine Integration Test With Dispenser Coin-Trigger Input
Prototype Bring-Up Pass Criteria
Prototype-Specific Warnings to Record