Pre-Layout Zone Classification — Smart CDI Motorcycle ECU
Final quick anomaly scan
Checked review categories:
- ERC floating pins
- ERC no-connect handling
- ERC shorted components
- ERC missing power pins
- ERC single-pin / undriven nets
- Missing PCB footprints
- Parts availability
- MPN and datasheet checks
Result: no open errors or warnings were reported by the queried checks.
Engineering notes before layout:
- The BOM metadata intentionally overrides several original library part names:
- Q1 library part name is
2N6509G, but approved BOM MPN is BT151-600R / TO-220 SCR equivalent.
- Q4 library part name is
IRFR420ATRPBF, but approved BOM MPN is IRFZ44N / TO-220 MOSFET equivalent.
- U3 library part name is
AP2112K-3.3TRG1, but approved BOM MPN is AMS1117-3.3 / SOT-223 equivalent.
- This is acceptable as a workshop/manual-BOM design decision, but footprints/pinouts must be visually verified before routing and fabrication.
- SG3525 timing values are provisional: R25 = 15kΩ, C12 = 1nF. Tune these on bench for the real transformer and target charge rate.
C_HV, T1, Q1, and U5 remain manual-approved safety-critical items; do not auto-substitute.
Power / High-Voltage Zone
Place these together in a physically isolated HV/power region with wide traces, creepage, and no digital routing through the zone.
Battery input and automotive protection
- J1 — 12 V battery input terminal, 5.08 mm THT
- D2 — S3M reverse/input diode path
- D1 — SMBJ15A TVS transient clamp
- L1 — 47uH input filter inductor
- C4 — 100nF protected 12 V bypass
- C5 — 10uF protected 12 V bulk/local bypass
- C11 — 100nF protected 12 V bypass
- C21 — 470uF protected 12 V bulk capacitor
- TP1 — 12V_PROTECTED test point
- R21 — 0Ω star-ground link between GND_POWER and digital return point near J1 negative
5 V buck / power conversion
- U2 — XL1509-5.0E1 buck regulator
- L2 — 100uH buck inductor, CD75 intent
- D9 — SS34 buck catch diode
- C6 — 220uF 5 V output bulk capacitor
- C7 — 100nF 5 V output bypass
- C8 — 10uF 5 V output capacitor
- TP2 — 5V_OUT test point
SG3525 / flyback charger primary
- U4_SG3525 — SG3525 PWM controller
- R22 — 22Ω IRFZ44N gate resistor
- R23 — 10kΩ IRFZ44N gate-source pulldown
- R25 — 15kΩ SG3525 RT timing resistor
- C12 — 1nF SG3525 CT timing capacitor
- C20 — 100nF SG3525 REF decoupling capacitor
- Q4 — IRFZ44N TO-220 flyback MOSFET, BOM override
- T1 — EE25 / validated CDI flyback transformer
- C19 — 10nF switch-node/snubber-related capacitor
Flyback secondary, CDI storage, SCR discharge
- D3 — US1M fast HV rectifier
- D4 — US1M HV clamp/freewheel/protection path
- C_HV — 1.5uF HV CDI film capacitor, manual THT/mechanical item
- Q1 — BT151-600R TO-220 SCR, BOM override
- R24 — 1kΩ SCR gate-cathode pulldown
- R8 — 100Ω opto/SCR gate resistor
- C13 — 10nF SCR gate/noise suppression capacitor
- U6 — MOC3021S opto trigger
- R7 — 220Ω opto LED input resistor
- J2 — coil output terminal, 5.08 mm THT
- TP4 — HV_FB test point
- TP5 — SCR_FIRE/GPIO27 trigger test point
- R18, R19, R20 — HV feedback divider / feedback network
Auxiliary low-side outputs, power side
- Q2 — AO3400A AUX1 low-side MOSFET
- Q3 — AO3400A AUX2 low-side MOSFET
- R14, R16 — 100Ω gate resistors
- R15, R17 — 10kΩ gate pulldowns
- D5, D6 — RS1M output protection diodes
- CN2 — auxiliary output connector
Digital / Control Zone
Place these in the low-voltage digital/control region. Keep them away from the flyback switch node, HV capacitor, SCR, coil connector, and transformer.
ESP32 core and programming
- U1 — ESP32-WROOM-32UE-N4
- J6 — PROG_UART 1x6 2.54 mm programming header
- SW1 — DIP/config switch
- SW2 — BOOT/IO0 switch
- SW3 — EN/reset switch
- R1 — 10kΩ EN pullup
- R2 — 10kΩ IO0/BOOT pullup
- R3, R4, R5, R6 — 10kΩ pullups/pulldowns for DIP/GPIO support
- C1 — 10uF 3V3 bulk near ESP32
- C2 — 100nF ESP32 local decoupling
- C3 — 1uF EN/reset/boot support capacitor
- C9 — 10uF regulator/output bulk near U3/ESP32
- C10 — 100nF ESP32/3V3 local decoupling
- C18 — 100nF digital local decoupling
- TP3 — 3V3 test point
3.3 V regulator
- U3 — AMS1117-3.3 metadata override / 3.3 V regulator
- C9, C10, C18 — local input/output bypassing for 3.3 V rail, final placement must match actual AMS1117 stability guidance
VR pickup interface and analog sensor input
- U5 — MAX9924 VR sensor interface, manual-approved safety-critical item
- J3 — VR pickup connector
- TP6 — VR_OUT / VR_PULSE test point
- C16 — 100nF MAX9924 VCC decoupling
- C17 — 10nF MAX9924 threshold/filter capacitor
- R12 — 2.2kΩ MAX9924/signal support resistor
- CN1 — sensor connector
- J5 — sensor connector / 5 V sensor power interface
- R9, R10 — TPS/sensor divider
- R11, R13 — analog input protection/filter resistors
- C14, C15 — analog input filter capacitors
- D7, D8 — BZT52C3V3 input clamps
- TP6 — VR output debug test point
Digital-side test/debug points
- TP2 — 5V_OUT test point, place near 5 V distribution but accessible from digital edge
- TP3 — 3V3 test point near ESP32/U3
- TP5 — GPIO27/SCR trigger scope point near ESP32 side of opto input
- TP6 — VR_OUT scope point near MAX9924 output
Components with mixed-boundary placement
These sit at the isolation boundary and should be oriented to keep current/noise flow one-way:
- U6 MOC3021S: LED/input side toward ESP32/digital; output/MT side toward SCR/power.
- R7: physically near U6 input pin and ESP32 GPIO27 trace; short trace to U6 LED.
- R8/R24/C13: physically near Q1 gate/cathode, not near ESP32.
- R21: physically at the single star point close to J1 pin 2 / battery negative. It is the only intentional GND_POWER-to-digital tie.
- TP4 HV_FB: accessible but physically outside the pure digital core; route divider output away from switch-node noise.
Mandatory physical-neighborhood instructions
Decoupling and regulator stability
- C16 must be directly beside U5 VCC/GND pins.
- C20 must be directly beside U4_SG3525 REF/GND pins.
- C12 and R25 must be close to U4_SG3525 CT/RT/DISCH pins with no long routing.
- C1/C2/C10/C18 should be distributed close to ESP32 3V3/GND pins; keep one 100nF as close as possible to U1.
- C9 and the required AMS1117 input/output capacitors must be placed tight to U3 pins. Verify the actual AMS1117 footprint/pinout and ESR/cap requirements before fabrication.
- C6/C7/C8 must be close to the 5 V buck output and U2/L2/D9 loop.
- C4/C5/C11/C21 must be close to the protected 12 V input distribution and flyback/buck feed.
High-current / switching loops
- R22 must sit directly at Q4 gate; the SG3525-to-R22 trace may be longer than R22-to-gate, but keep both short.
- R23 must sit directly between Q4 gate and source.
- Q4, T1 primary, C19/snubber components, and the 12 V input bulk capacitors must form the smallest practical loop.
- Keep FLYBACK_SWITCH copper short, wide where appropriate, and isolated from all ESP32/MAX9924/sensor traces.
- D3 must be close to T1 secondary and C_HV charge path; minimize HV loop area.
- C_HV, Q1, J2 coil output, and D4 must be clustered as the CDI discharge loop with short, wide HV traces.
- R24, R8, and C13 must sit close to Q1 gate/cathode.
Grounding / isolation
- Treat GND_POWER as the return for flyback, buck, SCR, coil, auxiliary outputs, and input protection.
- Treat digital return/GND as the return for ESP32, MAX9924, sensor conditioning, programming header, and logic switches.
- Join the two domains only through R21 at the battery negative/star point near J1 pin 2.
- Do not pour digital ground under the flyback switch node, transformer primary, SCR anode/cathode discharge loop, or coil output connector.
- Do not route MAX9924 input or ESP32 GPIO traces through the HV/power zone.
Connectors and mechanical placement
- J1 and J2 must sit at the board edge with mechanical clearance for 5.08 mm wiring.
- J3/CN1/J5 should sit on the sensor/digital edge, away from J2 coil output and transformer.
- J6 PROG_UART should sit near U1 but on an accessible board edge.
- T1 and C_HV need mechanical keepouts and mounting validation; do not crowd small SMD passives under/around their mechanical envelope.
Is it cleared for PCB mode?
Cleared for entering PCB placement mode with strict constraints:
- Use two hard zones: HV/power and digital/control.
- Place before routing; do not auto-route before manual/constraint-based placement.
- Preserve 6 mm clearance from HV/CDI nets to digital signals.
- Use 2.5 mm minimum on HV/CDI discharge nets, 1.0 mm on power rails, and 0.3 mm on logic/sensor traces as previously configured.
- Visually verify TO-220 pinouts for Q1/Q4 and SOT-223 pinout for U3 before routing.
- Bench-tune SG3525 timing/compensation values after first prototype.
Conclusion: the schematic is electrically clean enough to proceed to PCB placement, but not directly to final auto-routing/fabrication until the part-name/MPN override footprints and HV creepage are visually checked.