Custom ESP32-S3 Baseboard Design


Datasheet check is partly complete: the high-current P-MOSFET reverse-protection part is suitable for the 5A+ path, and the NPN driver part is suitable for GPIO gate/buzzer drive. I’m now selecting the safest electronic switch part for the three special floating A/B filter channels before adding the full schematic.
Progress made:
  • Renamed the project and updated the description.
  • Created/updated project files for the system architecture, GPIO map, external regulated 5V input, >5A power-path requirement, and external MAIN_POWER_SWITCH connector approach.
  • Added the main schematic components: ESP32-S3 44-pin DevKit placeholder, high-current P-MOS reverse-polarity MOSFET, 5V/12V screw terminals, servo/OLED/UART/TFT/INA226 connectors, normal MOSFET output hardware, buzzer, flyback diodes, and 3x solid-state MOS-output relay parts for the special filter channels.
  • Verified key datasheet points for the P-channel MOSFET and 2N3904 driver; the ESP32-S3 DevKit exact N16R8 footprint still must be confirmed before manufacturing.
Current state:
  • Components have been added, but the schematic is not wired yet.
  • No PCB layout has been started.
  • Review/ERC has not been run yet.
Remaining work:
  • Add passive parts: bulk capacitors, decoupling capacitors, I2C pull-ups, gate/base resistors, LED resistors, LC/RC filter components, and mounting holes.
  • Wire the 5V input path through reverse-polarity protection and MAIN_POWER_SWITCH, then split into SERVO_5V and LOGIC_5V.
  • Wire ESP32 GPIOs to servos, TFT, I2C, UART, buzzer, normal MOSFET outputs, and filter relay channels.
  • Wire the 3 special filter channels exactly per your A/B, C1/C2/R1, L1/L2, and MOSFET relay topology.
  • Run review/ERC and fix violations.
  • Confirm the exact ESP32-S3 N16R8 44-pin board footprint/pinout before layout/manufacturing.
Wire power tree
Use Option A
Add capacitors
Run ERC
Add mounting holes

U1
J_5V_OUT
J_INA_SENSE2
J_12V_IN
J_FILTER_CH3
J_INA1
J_OUT4
J_OUT3
J_INA_SENSE3
J_INA_SENSE1
J_INA2
J_OUT1
J_FILTER_CH1
J_MAIN_SW
J_INA3
J_OUT2
J_FILTER_CH2
J_PWR_IN
QOUT2
QOUT1
QDRV4
J_OLED
QOUT4
J_TFT
QBUZ1
QDRV1
J_UART2
QOUT3
QDRV3
QDRV2
J_SERVO1
TVS_CH2
J_SERVO3_EXT
BZ1
DOUT4
DOUT1
SSR_CH1
SSR_CH2
J_SERVO2
TVS_CH3
TVS_CH1
DOUT2
DOUT3
SSR_CH3
QRP1
ESP32-S3 Servo Load Controller - Project Specification
Scope
Robust ESP32-S3 N16R8 44-pin DevKit/baseboard for 3x MG90S servos, SPI ILI9341 TFT, I2C OLED, 3x INA226 plug-in modules, COM2 UART, active buzzer, normal 12 V MOSFET outputs, and 3x special 12 V two-core LC/RC filter relay channels.
Critical assumptions to verify before manufacturing
  1. Exact ESP32-S3 N16R8 44-pin DevKit pinout and mechanical footprint must be confirmed from the purchased board.
  2. TFT module must accept 3.3 V SPI logic when powered from 5 V.
  3. OLED and INA226 modules must not pull SDA/SCL to 5 V. Preferred board pull-ups are to 3.3 V only.
  4. Special filter relay switching behavior must be bench-tested on one channel: the provided topology is a filtered shunt/bridge between A and B after L1/L2, not a series interruption of one conductor.
  5. Main 5 V source is an external regulated 5 V DC adapter/module supplied by user. No onboard 5 V regulator is used for the main rail.
  6. Main power switching uses an external high-current panel-mount switch wired to a PCB connector labeled MAIN_POWER_SWITCH. Do not use a small low-current PCB slide switch in series with servo current.
  7. 5 V input path, switch loop, and servo branch must be sized for at least 5 A, preferably 6 A or more.
  8. Normal MOSFET output count is assumed as 4 channels unless revised; GPIOs planned: GPIO16, GPIO35, GPIO36, GPIO37.
  9. Use 2-layer PCB, 1 oz minimum, 2 oz preferred for servo/load current. Bottom layer is continuous GND plane with antenna copper keepout.
Functional blocks
  • Power input/protection: external regulated 5 V screw input, P-channel MOSFET reverse-polarity protection, external MAIN_POWER_SWITCH loop, protected/switched 5 V rails.
  • Servo power: separate high-current 5 V branch with 1000 uF bulk capacitor and local 100 nF capacitors.
  • Logic/module power: ESP32 VIN/5V, TFT/OLED/INA226/UART/buzzer/MOSFET gate pull-ups, 100 uF and local 10 uF/100 nF decoupling.
  • ESP32-S3 DevKit interface: 44-pin footprint/header with GPIO silkscreen labels and boot-sensitive pin restrictions.
  • Peripherals: SPI TFT, I2C OLED + 3x INA226, COM2 UART, buzzer driver.
  • Outputs: normal low-side MOSFET channels with inverted NPN gate drive and status LEDs.
  • Special filter relay channels: 3 identical LC/RC channels with A/B screw terminals, 2x 100 uH inductors >=2 A, 100 nF/50 V, 1 uF/50 V, 100 kOhm, MOSFET relay element, status LED.
GPIO allocation

Table


FunctionGPIO
Servo 1 PWMGPIO4
Servo 2 PWMGPIO5
Servo 3 external PWMGPIO6
TFT MOSIGPIO11
TFT SCLKGPIO12
TFT CSGPIO10
TFT DCGPIO9
TFT RSTGPIO8
I2C SDAGPIO21
I2C SCLGPIO47
COM2 TXGPIO17
COM2 RXGPIO18
BuzzerGPIO3
Filter relay CH1GPIO13
Filter relay CH2GPIO14
Filter relay CH3GPIO15
Normal MOSFET OUT1GPIO16
Normal MOSFET OUT2GPIO35
Normal MOSFET OUT3GPIO36
Normal MOSFET OUT4GPIO37
Layout rules to enforce later
  • ESP32 antenna at board edge with no copper/traces under antenna region on any layer.
  • Servo/high-current returns route back to power entry, not through ESP32/TFT/I2C/INA226 areas.
  • SPI SCLK short and away from MOSFET drains, filter channels, servo PWM, and high-current loops.
  • I2C and INA226 sense wiring away from 12 V switching/filter loops.
  • Servo +5 V traces/copper: preferred >=2 mm, absolute minimum 1.5 mm.
  • Logic 5 V traces >=0.5 mm; signals >=0.25 mm.
  • 12 V/load/filter/sense traces sized for real current; use copper pours where needed.
  • Scope

  • Critical assumptions to verify before manufacturing

  • Functional blocks

  • GPIO allocation

  • Layout rules to enforce later