The HY2120 Kelvin-sensing work completed, but I could not retrieve and reconcile its final report before execution ended.
Confirmed work from this session:
Added dedicated Kelvin branches from:
U6 VSS → RS1 BATT_NEG-side land
U6 CS/R38 → Q2 source land
Removed the previous remote sense branches.
Preserved component placement, USB routing, MOTOR_B Kelvin routing, high-current copper, and the 0.10 mm spacing rule.
Latest verified board state:
0 airwires
0 blocking DRC errors
17 intentional redundant-copper groups retained
The last reviewed qualification still had two unresolved release gates:
Proving isolation of the Q2 Kelvin pickup via from Bottom/Mid-Layer-2 load-current copper.
Conservatively bounding the internal RS1–Q1–Q2 copper resistance and confirming positive margin below the HY2120’s 170 mV minimum overcurrent threshold.
The final executor was specifically working on those two gates, but its result was not available for reconciliation. Therefore, the board is not yet approved for manufacturing, and no new manufacturing exports were generated.
Remaining work:
Retrieve and review the final Kelvin-sensing report.
Confirm the 10.565 A / 500 ms hot overcurrent margin.
Run an independent final ERC/DRC and protection-path review.
Verify JLCPCB BOM stock and via/stencil requirements.
Update firmware and bring-up documentation.
Regenerate Gerbers, BOM, CPL, STEP, PDF, and IPC-D-356 files.
Completed: low-cost battery-protection redesign, autonomous-startup correction, replacement of all six power MOSFETs with one stocked MPN, DRV8701 current-control corrections, support-passive wiring, sourcing review, power/protection calculations and schematic verification.
Completed, retained after review: BQ76907 monitor/balancer, DRV8701 H-bridge driver, AP63203 3.3 V buck, AP63205 5 V buck, USBLC6-2SC6 ESD arrays, connectors, ESP32-S3, TVS, shunts and external interfaces.
Unattempted by design: PCB placement and routing for newly added components. This review was limited to the schematic.
Implemented architecture
Autonomous 2S cutoff
U6 is ABLIC S-8252AAO-M6T1U / LCSC C468216, an inexpensive SOT-23-6 factory-autonomous 2S protector. It drives the existing back-to-back low-side AON7544 protection FETs without firmware:
R35 = 1 MΩ retains a default-off pull-down on the charge FET.
The datasheet specifies the DO/CO/VM/VC/VDD/VSS pinout, two external N-channel FET topology and recommended 150 Ω–1 kΩ cell resistors, 0.068–1.0 µF capacitors and 300 Ω–4 kΩ VM resistor.
The AAO suffix is documented as nominally 4.25 V/cell OV, 2.50 V/cell UV, +0.20 V discharge-overcurrent, +0.50 V short-circuit and −0.10 V charge-overcurrent, with 0 V charging inhibited. The exact suffix-table extraction was cited but not machine-verified, so confirm it against the released ABLIC ordering table before procurement lock.
This resolves the prior critical startup flaw: the ESP32 no longer needs to boot through FETs that first depend on a BQ76907 initialization command.
BQ76907 monitor and balancing subsystem
U2 remains BQ76907RGRR / LCSC C22458649, but its DSG and CHG outputs are intentionally no-connect. U2 now provides:
Two-cell voltage monitoring.
1 mΩ shunt current measurement/coulomb counting.
B3380 thermistor measurement.
I²C telemetry and ALERT.
Host-controlled balancing.
The real cell measurement pairs are VC7–VC6 and VC1–VC0, while VC6 through VC1 are shorted for two-cell operation. D4/R1/C1 and D5/R5/C26 provide the BAT/REGSRC filtering, C2 bypasses REGOUT, and R31/R32/C27 form the 100 Ω / 100 Ω / 100 nF Kelvin current-sense filter.
Firmware must initialize U2 for telemetry, alerts and balancing, but system power-up and primary cutoff no longer depend on FET_ENABLE. Balancing remains supervisory and is not a charger.
H-bridge and gate-drive corrections
U3 DRV8701 and RS2 = 2 mΩ were retained. Q3–Q6 are AON7544 / LCSC C315567, matching Q1/Q2 and reducing MOSFET-type count.
Two prior value errors were corrected:
R14 changed from 0 Ω to 33 kΩ, selecting approximately 12.5 mA source / 25 mA sink gate drive. The previous 6 mA setting could not charge the AON7544 maximum 22.5 nC gate charge within the DRV8701 typical drive interval.
The VREF divider changed to R12 = 100 kΩ, R13 = 10 kΩ, producing approximately 0.436 V and about 9.7 A typical current chopping with RS2 = 2 mΩ. The previous 110 kΩ/10 kΩ divider was only about 8.75 A.
AON7544 is rated 30 V and 30 A at TC = 25 °C. Low-pack gate enhancement, transient SOA and thermal rise still require bench validation.
Sourcing outcome
Table
Function
Decision
Selected part
Autonomous 2S cutoff
Added to guarantee safe startup without firmware
S-8252AAO-M6T1U, C468216
Monitor/coulomb counter/balancing
Retained but removed from primary gate control
BQ76907RGRR, C22458649
Six power MOSFETs
Standardized on one stocked MPN
AON7544, C315567
Motor driver
Retained; support values corrected
DRV8701PRGER, C114178
BMS supply diodes
Retained per BAT/REGSRC guidance
1N4148WS-R1_000A4, C268414
3.3 V / 5 V bucks
Retained
AP63203WU-7 / AP63205WU-7
USB/UART ESD
Retained
USBLC6-2SC6
The added protector is an Extended JLCPCB part, but its component cost is low and it prevents dependence on production OTP/NV configuration for initial pack connection.
Firmware impact
Initialize BQ76907 for measurements, ALERT behavior, thermistor mode and balancing; do not attempt to use its DSG/CHG pins.
Treat U6 as the independent hardware cutoff and report its action indirectly through loss of SYS_GND or BQ/driver observations.
Do not permit motor pulses until U2 reports plausible cells and temperature.
Use 6.6 V loaded-pack as the initial motor-inhibit threshold; U6's 2.50 V/cell UV is a last-resort protection limit, not an actuator operating threshold.
Preserve bridge safe-state behavior: disabled at boot, neutral before reversal, nFAULT/BMS alert latching and a hard pulse timeout no longer than 0.5 s.
Verification evidence
Live schematic inspection confirms U6 VDD/VC matched RC filters, VSS reference before Q1, VM sense after Q2, autonomous DO/CO gate paths and no-connects on U2 DSG/CHG.
Live inspection confirms Q1/Q2 remain back-to-back in the BATT_NEG-to-SYS_GND return path and BQ76907 retains its cell, thermistor, I²C and Kelvin shunt connections.
ERC/passive/schematic review returned no open errors, warnings or uncertain checks after the final rewiring.
Current schematic count after the redesign is 95 components; no PCB layout operation was executed.
Remaining uncertainties and required validation
Confirm the exact S-8252AAO suffix thresholds/delays and 0 V charging behavior against the procurement revision of the ABLIC datasheet.
Verify the U6 + Q1/Q2 discharge-overcurrent trip remains above the normal 10 A / 0.5 s pulse at low pack voltage, cold cells and worst repeated-duty heating.
Verify Q1/Q2 power up enabled for healthy cells without MCU action and recover correctly after UV, OV, overload and charger insertion/removal.
Validate actuator sag, DRV8701 VM margin, AON7544 gate waveforms, shoot-through, transient junction rise and 30 V VDS margin.
Use an external suitable 2S CC/CV charger; neither U6 nor U2 is the charger.
Place and route U6, R36–R38 and C28–C29 in the later PCB phase. Keep the cell-filter loop compact and the VM/VSS sensing references away from motor-current switching copper.