The HY2120 Kelvin-sensing work completed, but I could not retrieve and reconcile its final report before execution ended.
Confirmed work from this session:
Added dedicated Kelvin branches from:
U6 VSS → RS1 BATT_NEG-side land
U6 CS/R38 → Q2 source land
Removed the previous remote sense branches.
Preserved component placement, USB routing, MOTOR_B Kelvin routing, high-current copper, and the 0.10 mm spacing rule.
Latest verified board state:
0 airwires
0 blocking DRC errors
17 intentional redundant-copper groups retained
The last reviewed qualification still had two unresolved release gates:
Proving isolation of the Q2 Kelvin pickup via from Bottom/Mid-Layer-2 load-current copper.
Conservatively bounding the internal RS1–Q1–Q2 copper resistance and confirming positive margin below the HY2120’s 170 mV minimum overcurrent threshold.
The final executor was specifically working on those two gates, but its result was not available for reconciliation. Therefore, the board is not yet approved for manufacturing, and no new manufacturing exports were generated.
Remaining work:
Retrieve and review the final Kelvin-sensing report.
Confirm the 10.565 A / 500 ms hot overcurrent margin.
Run an independent final ERC/DRC and protection-path review.
Verify JLCPCB BOM stock and via/stencil requirements.
Update firmware and bring-up documentation.
Regenerate Gerbers, BOM, CPL, STEP, PDF, and IPC-D-356 files.
Historical layout/model record: Later pad-datum route changes and their unresolved qualification gates are documented in HY2120 Kelvin Routing Review. The pickup geometry below is no longer the live geometry. The 1.686 mΩ table below does not separately bound the internal RS1-to-Q1 source bus and Q1-to-Q2 drain bridge; it must not be reused as a complete post-Kelvin resistance model. The design remains unqualified for manufacturing.
Conclusion
UNQUALIFIED for 10.565 A / 500 ms against a 170 mV minimum OCD threshold.
The post-change conservative geometric upper-bound model gives 1.686 mΩ PCB/interconnect resistance at 20°C, 2.547377 mΩ at 150°C, and 172.476292 mV total sensed voltage at 10.565 A. This is 2.476292 mV above the 170 mV comparison limit before adding switching noise, connector/contact variation, copper-fabrication variation, current crowding, or unequal via sharing.
The board therefore does not have defensible nuisance-trip margin. The 500 ms pulse duration does not rescue the result because HY2120 OCD delay is much shorter than 500 ms.
U6 VSS currently reaches the BATT_NEG network through a local via at (3.6000, 20.8594) mm. This is near U6, not at the RS1 terminal, so it is not a true RS1 Kelvin pickup.
RS1 BATT_NEG pad center: (15.27, 20.43) mm; pad is 2.0 × 3.3 mm.
RS1 opposite pad center: (15.27, 26.57) mm.
Q1/Q2 common-drain bridge: Top copper rectangle 4.3 × 3.2 mm, centered at (10.0, 22.1) mm.
Q2 source pads: (8.09, 15.64), (9.37, 15.64), (10.64, 15.64) mm.
R38 SYS_GND pad: (3.99, 19.00) mm. Its branch joins the main Q2-to-SYS_GND network at approximately (4.614463, 19.624463) mm.
R38-to-U6 CS is a signal-current path and does not materially add load-current drop after the SYS_GND pickup.
Therefore the sensed voltage includes RS1, both MOSFET channels, and the load-current copper between the BATT_NEG pickup and RS1 plus the load-current copper between Q2 source and the SYS_GND pickup.
Live high-current geometry
BATT_NEG side
Existing 2.0 mm Top/Bottom trunk near RS1 and J2.
Existing irregular broad BATT_NEG polygon from the J2 region to the RS1 via landing.
RS1 Top via landing: 4.7 × 1.8 mm, centered (16.35, 20.9) mm.
Via field uses 0.6 mm pads / 0.3 mm drills; the visible reinforcement is a nominal nine-via local array, with additional BATT_NEG vias elsewhere.
The broad polygon originally existed only on Mid-Layer 1. It was changed in this qualification to exist on Mid-Layer 1 and Bottom.
Q2-to-SYS_GND side
Q2 source Top landing: 3.2 × 2.2 mm, centered (9.4, 15.0) mm.
Local source traces include 0.75 mm fingers and a 1.5 mm trunk.
The broad return polygon already exists on Bottom and Mid-Layer 2.
Receiving landing: 1.8 × 1.4 mm, centered (3.35, 13.25) mm.
Local via field uses 0.6 mm pads / 0.3 mm drills and is treated as a nominal nine-via array.
Preserved geometry
Protected USB breakout copper was not edited.
Motor-current copper was not edited.
MOTOR_B Kelvin branch remains present as 0.254 mm Mid-Layer-2 copper, including the preserved branch segments and layer transitions.
No component was moved; anchors, U1, board outline, stackup, and spacing constraint were preserved.
Resistance model
Constants and fixed electrical assumptions
Load current: 10.565 A.
Copper thickness: 35 µm.
Copper resistivity at 20°C: 1.724×10⁻⁸ Ω·m.
35 µm sheet resistance: 0.492571 mΩ/square.
Copper 150°C multiplier: 1.5109.
RS1 hot/tolerance model: 6.097875 mΩ.
AON6512 engineering hot envelope: 3.84 mΩ each, 7.68 mΩ total. This is a 1.6× engineering margin from the verified 2.4 mΩ 25°C maximum at VGS = 4.5 V; it is not a manufacturer-guaranteed hot maximum.
HY2120 comparison threshold: 170 mV minimum.
Upper-bound assumptions
The CAD data exposes exact polygon outlines, trace widths, layer count, pad locations, and via drill/pad dimensions, but it does not solve the distributed 2-D current density. The model therefore uses deliberately conservative effective widths and includes current crowding/pad/via allowances:
Copper paths are reduced to distributed sheet-resistance branches using actual path lengths and conservative effective widths.
Broad parallel copper is counted only when it is continuously connected across the modeled section.
The 2.0 mm trunk is treated as a parallel branch only where it provides a distinct end-to-end path.
Via resistance uses the 1.3 mm board thickness and a conservative plated-barrel allowance, then adds unequal-sharing/current-spreading margin.
Pad and solder-spreading allowances are included; connector resistance outside the VSS-to-CS sensed boundaries is not included.
Baseline before the local copper change
Table
Section
Conservative 20°C upper bound
BATT_NEG pickup → RS1, including single-layer broad polygon, 2 mm trunk parallelism, landing, pad spreading, and via array
1.41 mΩ
Q2 source → SYS_GND pickup, including source fingers, broad Bottom/Mid2 return, 1.5 mm branch parallelism, landing, and via array
The BATT_NEG broad polygon is now duplicated on Bottom, in parallel with Mid-Layer 1. Accounting for the existing 2.0 mm trunk, via array, landing, current spreading, and unequal branch sharing:
Table
Section
Conservative 20°C upper bound
BATT_NEG pickup → RS1 after Bottom-layer polygon addition
0.936 mΩ
Q2 source → SYS_GND pickup
0.750 mΩ
Total PCB/interconnect
1.686 mΩ
Post-change hot-equivalent PCB resistance:
1.686 × 1.5109 = 2.5473774 mΩ
Post-change total sensed resistance:
6.097875 + 7.68 + 2.5473774 = 16.3252524 mΩ
Post-change sensed voltage:
10.565 A × 16.3252524 mΩ = 172.4762916 mV
Margin to 170 mV: −2.4762916 mV.
For reference, using the hot RS1/FET assumptions but keeping PCB copper at 20°C gives 163.375839 mV; this is not the required hot comparison and does not qualify the design.
Exact PCB changes made
Changed polygon BATT_NEG parallel Mid1 return bus (56ea9834-2506-4803-a2a1-a8c87ab345b3) from connectedLayers = Mid-Layer 1 to Mid-Layer 1,Bottom. Shape and placement were unchanged.
Removed the prior four-segment local U6 VSS branch and regenerated a 0.15 mm connection. The router reconnected U6 VSS to the same local BATT_NEG via at (3.6000, 20.8594) mm, with a reported route length of 1.057447 mm. This restored connectivity but did not relocate the pickup to RS1, so no Kelvin-credit was taken in the model.
No other PCB copper was changed.
Redundant-copper classification
Final DRC reports 18 redundant connected groups / 23 nodes. None is classified as removable debris:
Redundant copper: 18 warning groups / 23 nodes, all classified intentional as above.
Protected USB copper: preserved; protected USB redundant group intentionally retained.
MOTOR_B Kelvin branch: present and unchanged as 0.254 mm Mid-Layer-2 routing.
Board: unchanged 40 × 75 mm, Standard 4 Layer, 35 µm copper.
Mandatory next decision
Do not release this design on the present 170 mV-minimum comparison.
The next required design action is a controlled Kelvin rework that makes:
U6 VSS pick up directly at the RS1 BATT_NEG terminal/landing, and
R38 SYS_GND pick up directly at the Q2 source landing,
while removing the old remote pickup branches so the new Kelvin traces cannot become parallel load-current paths. After that edit, re-extract geometry and repeat this calculation and DRC. If those pickups cannot be isolated and routed safely without violating the fixed layout constraints, the protection device/current-threshold architecture must be changed; additional broad copper alone does not provide defensible margin in this geometry.