IoT Fire Alarm Device Design

flux

You should ask Quectel / supplier for the EC25MXGA hardware design package, not just the marketing datasheet.
Ask for:
  1. EC25MXGA Hardware Design Guide
    • Full pin descriptions
    • Power supply requirements
    • PWRKEY / RESET timing
    • UART / USB / SIM / RF reference circuits
    • VDD_SDIO usage guidance
  2. Recommended PCB land pattern / footprint
    • Pad dimensions
    • Pad numbering
    • Paste mask / solder mask recommendations
    • Keepout zones under/around the module
    • Assembly notes
  3. Reference schematic
    • VBAT_RF / VBAT_BB decoupling
    • SIM socket wiring
    • Antenna matching / ESD
    • Status pins
    • Power-on/off sequence
  4. RF layout guidelines
    • 50 Ω antenna routing
    • Ground stitching via recommendations
    • Antenna connector/matching network placement
    • Diversity/GNSS pins if used or unused
  5. Certification documents
    • RCM / ACMA / AS/CA S042 relevance
    • Carrier approval info for Australia
    • LTE band support for AU carriers
    • Test reports if available
  6. Lifecycle / supply confirmation
    • Active production status
    • Recommended replacement if EC25MXGA is not preferred
    • Minimum order / lead time
Short message you can send:
We are designing a dual-modem Australian fire alarm signalling device using 2 × EC25MXGA. Please provide the EC25MXGA hardware design guide, recommended PCB land pattern/footprint, reference schematic, RF layout guide, SIM interface recommendations, VDD_SDIO connection guidance, Australian carrier/certification documentation, and lifecycle/supply status.
D

drewmoutney

Ok I’ll contact them

flux

Good plan. Ask them specifically for the hardware design guide + recommended PCB land pattern for EC25MXGA-128-SNNS.
Until we get that, the safest path is:
  • Keep EC25MXGA in the design.
  • Do not send the PCB to manufacture yet.
  • Continue with placement/routing cleanup only as a draft.
  • Finalize modem footprint, SIM wiring, RF layout, and VDD_SDIO treatment once Quectel confirms the official guidance.
Clean draft layout
Review EC25 wiring
Check power budget
Update factory checklist
Run current checks
Sign up to send

Files

Schematic

Layout

Preview

Sealed Resistor Pack First-Pass Values
Decision
Use the existing AS-style analog voltage bands as the firmware decode target for all 8 supervised inputs. The sealed resistor pack will be designed so each Alarm/Fault/Isolate contact combination produces a voltage near the middle of its valid band.
Target decode table

Table

ConditionValid band at ASE inputFirst-pass target voltage
Short circuit0.000–0.196 V0.10 V
Normal0.38–0.82 V0.60 V
Isolate1.05–1.39 V1.20 V
Fault1.61–1.84 V1.72 V
Isolate + Fault1.98–2.12 V2.05 V
Alarm2.17–2.33 V2.25 V
Alarm + Isolate2.44–2.59 V2.52 V
Alarm + Fault2.68–2.80 V2.74 V
Alarm + Fault + Isolate2.86–3.02 V2.94 V
Open circuit5.00 V typical5.00 V
Hardware approach
  • Each field input channel uses protected analog sensing into an STM32 ADC.
  • Each external FAS interface uses a sealed resistor pack/EOL assembly so installers cannot alter individual resistor values.
  • The PCB should include input protection, RC filtering, and ADC source impedance low enough for stable STM32 conversion.
  • Firmware should apply debounce/filtering and classify readings using guard bands, not exactly at the threshold edges.
Still required
  • Calculate actual resistor values after the exact excitation/pull-up source and ADC divider are finalized.
  • Tolerance stack-up must include resistor tolerance, ADC reference tolerance, input leakage, cable resistance, noise, and temperature.
  • For compliance testing, document the final nominal voltages and worst-case min/max for each state.

  • Decision

  • Target decode table

  • Hardware approach

  • Still required