IoT Fire Alarm Device Design

flux

You should ask Quectel / supplier for the EC25MXGA hardware design package, not just the marketing datasheet.
Ask for:
  1. EC25MXGA Hardware Design Guide
    • Full pin descriptions
    • Power supply requirements
    • PWRKEY / RESET timing
    • UART / USB / SIM / RF reference circuits
    • VDD_SDIO usage guidance
  2. Recommended PCB land pattern / footprint
    • Pad dimensions
    • Pad numbering
    • Paste mask / solder mask recommendations
    • Keepout zones under/around the module
    • Assembly notes
  3. Reference schematic
    • VBAT_RF / VBAT_BB decoupling
    • SIM socket wiring
    • Antenna matching / ESD
    • Status pins
    • Power-on/off sequence
  4. RF layout guidelines
    • 50 Ω antenna routing
    • Ground stitching via recommendations
    • Antenna connector/matching network placement
    • Diversity/GNSS pins if used or unused
  5. Certification documents
    • RCM / ACMA / AS/CA S042 relevance
    • Carrier approval info for Australia
    • LTE band support for AU carriers
    • Test reports if available
  6. Lifecycle / supply confirmation
    • Active production status
    • Recommended replacement if EC25MXGA is not preferred
    • Minimum order / lead time
Short message you can send:
We are designing a dual-modem Australian fire alarm signalling device using 2 × EC25MXGA. Please provide the EC25MXGA hardware design guide, recommended PCB land pattern/footprint, reference schematic, RF layout guide, SIM interface recommendations, VDD_SDIO connection guidance, Australian carrier/certification documentation, and lifecycle/supply status.
D

drewmoutney

Ok I’ll contact them

flux

Good plan. Ask them specifically for the hardware design guide + recommended PCB land pattern for EC25MXGA-128-SNNS.
Until we get that, the safest path is:
  • Keep EC25MXGA in the design.
  • Do not send the PCB to manufacture yet.
  • Continue with placement/routing cleanup only as a draft.
  • Finalize modem footprint, SIM wiring, RF layout, and VDD_SDIO treatment once Quectel confirms the official guidance.
Clean draft layout
Review EC25 wiring
Check power budget
Update factory checklist
Run current checks
Sign up to send

Files

Schematic

Layout

Preview

Schematic Capture Status — Power Block
Completed in schematic
Added and wired the first power-stage components:
  • J1: 2-position 5.08 mm field power input terminal.
  • D1: SMBJ24A TVS for input transient protection.
  • U1: LTC4368 input protection controller for OV/UV/reverse-supply protection.
  • Q1/Q2: PSMN5R2-60YLX 60 V N-channel MOSFETs as back-to-back input protection pass FETs.
  • U2: LM46002-Q1 class buck for 3.3 V system rail.
  • U3/U4: LM46002 placeholders for Modem A/B 4.0 V rails.
  • L1-L3: 4.7 µH high-current buck inductors.
  • C1-C4: 100 µF bulk capacitors for input and output rails.
  • C11-C13: 100 nF bootstrap capacitors.
  • C14-C16: 100 nF VCC bypass capacitors.
  • C17-C19: 10 nF soft-start capacitors.
  • R1-R3: PGOOD pull-ups.
  • R4/R5/R20: RT timing resistor placeholders.
  • R9-R12: LTC4368 UV/OV threshold divider placeholders.
  • R13: LTC4368 fault pull-up.
  • R14-R19: regulator feedback divider placeholders.
Nets created/wired
  • VIN_RAW
  • PROTECT_FET_COMMON
  • PROTECT_FET_GATE
  • VIN_PROTECTED
  • 3V3_SYS
  • 4V0_MODEM_A
  • 4V0_MODEM_B
  • SW_3V3
  • SW_MODEM_A
  • SW_MODEM_B
  • FB_3V3
  • FB_MODEM_A
  • FB_MODEM_B
  • PGOOD_3V3
  • PGOOD_MODEM_A
  • PGOOD_MODEM_B
  • PWR_PROTECT_FAULT_N
  • GND
Verification status
A focused ERC/component check was run after wiring and removing unused placeholders. No matching ERROR/WARNING/OPEN checks were returned for the selected ERC/component review categories at that point.
Important caveats
  • U3/U4 are still placeholders: LM63440-Q1 was not found in the current Flux library. Replace U3/U4 with LM63440-Q1 or another documented 4 A modem buck before final PCB design.
  • UV/OV divider, RT, soft-start, and feedback values are provisional and must be calculated against the exact selected IC datasheets.
  • LTC4368 MOSFET orientation and sense topology should be checked against the datasheet/reference schematic before layout.
  • The modem rails are schematic-planning complete, not final power-design complete.
Next schematic step
Proceed to the STM32H757 core block: MCU, decoupling, reset/boot, SWD, USB-C programming/service, oscillator/RTC, and initial power-good/fault monitoring inputs.

  • Completed in schematic

  • Nets created/wired

  • Verification status

  • Important caveats

  • Next schematic step